// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_dcache.v
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// FT64_dcache.v
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// - a simple direct mapped cache
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// - a simple direct mapped cache
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// - three cycle latency
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// - three cycle latency
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module FT64_dcache(rst, dce, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, rhit);
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module FT64_dcache(rst, dce, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, rhit);
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input rst;
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input rst;
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input dce; // data cache enable
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input dce; // data cache enable
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [7:0] sel;
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input [31:0] sel;
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input [37:0] wadr;
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input [37:0] wadr;
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output whit;
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output whit;
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input [63:0] i;
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input [255:0] i;
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input [255:0] li; // line input
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input [255:0] li; // line input
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input rclk;
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input rclk;
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input [2:0] rdsize;
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input [2:0] rdsize;
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input [37:0] radr;
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input [37:0] radr;
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output reg [63:0] o;
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output reg [63:0] o;
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output reg [255:0] lo; // line out
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output reg [255:0] lo; // line out
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output reg rhit;
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output reg rhit;
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parameter byt = 3'd0;
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parameter byt = 3'd0;
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parameter wyde = 3'd1;
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parameter wyde = 3'd1;
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parameter tetra = 3'd2;
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parameter tetra = 3'd2;
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parameter octa = 3'd3;
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parameter octa = 3'd3;
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wire [255:0] dc;
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wire [255:0] dc;
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wire [31:0] v;
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wire [31:0] v;
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wire rhita;
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wire rhita;
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dcache_mem u1 (
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dcache_mem u1 (
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.rst(rst),
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.rst(rst),
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.clka(wclk),
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.clka(wclk),
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.ena(dce & wr),
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.ena(dce & wr),
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.wea(sel),
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.wea(sel),
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.addra(wadr[13:0]),
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.addra(wadr[13:0]),
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.dina(i),
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.dina(i),
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.clkb(rclk),
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.clkb(rclk),
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.enb(dce),
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.enb(dce),
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.addrb(radr[13:0]),
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.addrb(radr[13:0]),
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.doutb(dc),
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.doutb(dc),
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.ov(v)
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.ov(v)
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);
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);
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FT64_dcache_tag u3
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FT64_dcache_tag u3
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(
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(
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.wclk(wclk),
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.wclk(wclk),
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.dce(dce),
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.dce(dce),
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.wr(wr && wadr[4:3]==2'b11),
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.wr(wr),
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.wadr(wadr),
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.wadr(wadr),
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.rclk(rclk),
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.rclk(rclk),
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.radr(radr),
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.radr(radr),
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.whit(whit),
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.whit(whit),
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.rhit(rhita)
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.rhit(rhita)
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);
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);
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wire [7:0] va = v >> radr[4:0];
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wire [7:0] va = v >> radr[4:0];
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always @(posedge rclk)
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always @(posedge rclk)
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begin
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begin
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case(rdsize)
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case(rdsize)
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byt: rhit <= rhita & va[ 0];
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byt: rhit <= rhita & va[ 0];
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wyde: rhit <= rhita & &va[1:0];
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wyde: rhit <= rhita & &va[1:0];
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tetra: rhit <= rhita & &va[3:0];
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tetra: rhit <= rhita & &va[3:0];
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default:rhit <= rhita & &va[7:0];
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default:rhit <= rhita & &va[7:0];
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endcase
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endcase
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end
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end
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// hit is also delayed by a clock already
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// hit is also delayed by a clock already
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always @(posedge rclk)
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always @(posedge rclk)
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lo <= dc;
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lo <= dc;
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always @(posedge rclk)
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always @(posedge rclk)
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o <= dc >> {radr[4:3],6'b0};
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o <= dc >> {radr[4:3],6'b0};
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endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module dcache_mem(rst, clka, ena, wea, addra, dina, clkb, enb, addrb, doutb, ov);
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module dcache_mem(rst, clka, ena, wea, addra, dina, clkb, enb, addrb, doutb, ov);
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input rst;
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input rst;
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input clka;
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input clka;
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input ena;
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input ena;
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input [7:0] wea;
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input [31:0] wea;
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input [13:0] addra;
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input [13:0] addra;
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input [63:0] dina;
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input [255:0] dina;
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input clkb;
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input clkb;
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input enb;
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input enb;
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input [13:0] addrb;
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input [13:0] addrb;
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output reg [255:0] doutb;
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output reg [255:0] doutb;
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output reg [31:0] ov;
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output reg [31:0] ov;
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reg [255:0] mem [0:511];
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reg [255:0] mem [0:511];
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reg [31:0] valid [0:511];
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reg [31:0] valid [0:511];
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reg [255:0] doutb1;
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reg [255:0] doutb1;
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reg [31:0] ov1;
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reg [31:0] ov1;
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integer n;
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integer n;
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initial begin
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initial begin
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for (n = 0; n < 512; n = n + 1)
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for (n = 0; n < 512; n = n + 1)
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valid[n] = 32'h00;
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valid[n] = 32'h00;
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end
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end
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genvar g;
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genvar g;
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generate begin
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generate begin
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for (g = 0; g < 4; g = g + 1)
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for (g = 0; g < 32; g = g + 1)
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always @(posedge clka)
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always @(posedge clka)
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begin
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begin
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if (ena & wea[0] & addra[4:3]==g) mem[addra[13:5]][g*64+7:g*64] <= dina[7:0];
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if (ena & wea[g]) mem[addra[13:5]][g*8+7:g*8] <= dina[g*8+7:g*8];
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if (ena & wea[1] & addra[4:3]==g) mem[addra[13:5]][g*64+15:g*64+8] <= dina[15:8];
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if (ena & wea[g]) valid[addra[13:5]][g] <= 1'b1;
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if (ena & wea[2] & addra[4:3]==g) mem[addra[13:5]][g*64+23:g*64+16] <= dina[23:16];
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if (ena & wea[3] & addra[4:3]==g) mem[addra[13:5]][g*64+31:g*64+24] <= dina[31:24];
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if (ena & wea[4] & addra[4:3]==g) mem[addra[13:5]][g*64+39:g*64+32] <= dina[39:32];
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if (ena & wea[5] & addra[4:3]==g) mem[addra[13:5]][g*64+47:g*64+40] <= dina[47:40];
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if (ena & wea[6] & addra[4:3]==g) mem[addra[13:5]][g*64+55:g*64+48] <= dina[55:48];
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if (ena & wea[7] & addra[4:3]==g) mem[addra[13:5]][g*64+63:g*64+56] <= dina[63:56];
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if (ena & wea[0] & addra[4:3]==g) valid[addra[13:5]][g*8] <= 1'b1;
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if (ena & wea[1] & addra[4:3]==g) valid[addra[13:5]][g*8+1] <= 1'b1;
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if (ena & wea[2] & addra[4:3]==g) valid[addra[13:5]][g*8+2] <= 1'b1;
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if (ena & wea[3] & addra[4:3]==g) valid[addra[13:5]][g*8+3] <= 1'b1;
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if (ena & wea[4] & addra[4:3]==g) valid[addra[13:5]][g*8+4] <= 1'b1;
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if (ena & wea[5] & addra[4:3]==g) valid[addra[13:5]][g*8+5] <= 1'b1;
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if (ena & wea[6] & addra[4:3]==g) valid[addra[13:5]][g*8+6] <= 1'b1;
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if (ena & wea[7] & addra[4:3]==g) valid[addra[13:5]][g*8+7] <= 1'b1;
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @(posedge clkb)
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always @(posedge clkb)
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if (enb)
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if (enb)
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doutb1 <= mem[addrb[13:5]];
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doutb1 <= mem[addrb[13:5]];
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always @(posedge clkb)
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always @(posedge clkb)
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if (enb)
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if (enb)
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doutb <= doutb1;
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doutb <= doutb1;
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always @(posedge clkb)
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always @(posedge clkb)
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if (enb)
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if (enb)
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ov1 <= valid[addrb[13:5]];
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ov1 <= valid[addrb[13:5]];
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always @(posedge clkb)
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always @(posedge clkb)
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if (enb)
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if (enb)
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ov <= ov1;
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ov <= ov1;
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endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module FT64_dcache_tag(wclk, dce, wr, wadr, rclk, radr, whit, rhit);
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module FT64_dcache_tag(wclk, dce, wr, wadr, rclk, radr, whit, rhit);
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input wclk;
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input wclk;
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input dce; // data cache enable
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input dce; // data cache enable
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input wr;
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input wr;
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input [37:0] wadr;
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input [37:0] wadr;
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input rclk;
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input rclk;
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input [37:0] radr;
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input [37:0] radr;
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output reg whit; // write hit
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output reg whit; // write hit
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output reg rhit; // read hit
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output reg rhit; // read hit
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wire [31:0] rtago;
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wire [31:0] rtago;
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wire [31:0] wtago;
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wire [31:0] wtago;
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FT64_dcache_tag2 u1 (
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FT64_dcache_tag2 u1 (
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.clka(wclk),
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.clka(wclk),
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.ena(dce),
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.ena(dce),
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.wea(wr),
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.wea(wr),
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.addra(wadr[13:5]),
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.addra(wadr[13:5]),
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.dina(wadr[37:14]),
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.dina(wadr[37:14]),
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.douta(wtago),
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.douta(wtago),
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.clkb(rclk),
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.clkb(rclk),
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.web(1'b0),
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.web(1'b0),
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.dinb(32'd0),
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.dinb(32'd0),
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.enb(dce),
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.enb(dce),
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.addrb(radr[13:5]),
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.addrb(radr[13:5]),
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.doutb(rtago)
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.doutb(rtago)
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);
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);
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always @(posedge rclk)
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always @(posedge rclk)
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rhit <= rtago[23:0]==radr[37:14];
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rhit <= rtago[23:0]==radr[37:14];
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always @(posedge wclk)
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always @(posedge wclk)
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whit <= wtago[23:0]==wadr[37:14];
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whit <= wtago[23:0]==wadr[37:14];
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endmodule
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endmodule
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