| Line 1... |
Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_idecoder.v
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// FT64_idecoder.v
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| Line 46... |
Line 46... |
// Memory access sizes
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// Memory access sizes
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parameter byt = 3'd0;
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parameter byt = 3'd0;
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parameter wyde = 3'd1;
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parameter wyde = 3'd1;
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parameter tetra = 3'd2;
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parameter tetra = 3'd2;
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parameter octa = 3'd3;
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parameter octa = 3'd3;
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parameter hexi = 3'd4;
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|
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// Really IsPredictableBranch
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// Really IsPredictableBranch
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// Does not include BccR's
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// Does not include BccR's
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//function IsBranch;
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//function IsBranch;
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//input [47:0] isn;
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//input [47:0] isn;
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| Line 95... |
Line 96... |
endcase
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endcase
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else
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else
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IsALU = TRUE;
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IsALU = TRUE;
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`BRK: IsALU = FALSE;
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`BRK: IsALU = FALSE;
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`Bcc: IsALU = FALSE;
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`Bcc: IsALU = FALSE;
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`BLcc: IsALU = FALSE;
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`BBc: IsALU = FALSE;
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`BBc: IsALU = FALSE;
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`BEQI: IsALU = FALSE;
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`BEQI: IsALU = FALSE;
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`BNEI: IsALU = FALSE;
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`CHK: IsALU = FALSE;
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`CHK: IsALU = FALSE;
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`JAL: IsALU = FALSE;
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`JAL: IsALU = FALSE;
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`JMP: IsALU = FALSE;
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`JMP: IsALU = FALSE;
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`CALL: IsALU = FALSE;
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`CALL: IsALU = FALSE;
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`RET: IsALU = FALSE;
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`RET: IsALU = FALSE;
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| Line 176... |
Line 179... |
`R2: case(instr[`INSTRUCTION_S2])
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`R2: case(instr[`INSTRUCTION_S2])
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`RTI: IsFlowCtrl <= TRUE;
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`RTI: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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default: IsFlowCtrl <= FALSE;
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endcase
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endcase
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`Bcc: IsFlowCtrl <= TRUE;
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`Bcc: IsFlowCtrl <= TRUE;
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`BLcc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BEQI: IsFlowCtrl <= TRUE;
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`BEQI: IsFlowCtrl <= TRUE;
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`BNEI: IsFlowCtrl <= TRUE;
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`CHK: IsFlowCtrl <= TRUE;
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`CHK: IsFlowCtrl <= TRUE;
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`JAL: IsFlowCtrl <= TRUE;
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`JAL: IsFlowCtrl <= TRUE;
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`JMP: IsFlowCtrl <= TRUE;
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`JMP: IsFlowCtrl <= TRUE;
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`CALL: IsFlowCtrl <= TRUE;
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`CALL: IsFlowCtrl <= TRUE;
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`RET: IsFlowCtrl <= TRUE;
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`RET: IsFlowCtrl <= TRUE;
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| Line 248... |
Line 253... |
default: fnCanException = FALSE;
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default: fnCanException = FALSE;
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endcase
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endcase
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// Had branches that could exception if looping to self. But in a tight loop
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// Had branches that could exception if looping to self. But in a tight loop
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// it affects store performance.
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// it affects store performance.
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// -> A branch may only exception if it loops back to itself.
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// -> A branch may only exception if it loops back to itself.
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`Bcc,`BBc,`BEQI: fnCanException = isn[7] ? brdisp == 11'h7FF : brdisp == 11'h7FE;
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`Bcc,`BLcc,`BBc,`BEQI,`BNEI: fnCanException = isn[7] ? brdisp == 11'h7FF : brdisp == 11'h7FE;
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`CHK: fnCanException = TRUE;
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`CHK: fnCanException = TRUE;
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default:
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default:
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// Stores can stil exception if there is a write buffer, but we allow following
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// Stores can stil exception if there is a write buffer, but we allow following
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// stores to be issued by ignoring the fact they can exception because the stores
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// stores to be issued by ignoring the fact they can exception because the stores
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// can be undone by invalidating the write buffer.
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// can be undone by invalidating the write buffer.
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`ifdef HAS_WB
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`ifdef HAS_WB
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fnCanException = IsMem(isn) && !IsStore(isn);
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fnCanException = IsMem && !IsStore(isn);
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`else
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`else
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fnCanException = IsMem(isn);
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fnCanException = IsMem;
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`endif
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`endif
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endcase
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endcase
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end
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end
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endfunction
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endfunction
|
|
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| Line 279... |
Line 284... |
`LVxU: IsLoad = TRUE;
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`LVxU: IsLoad = TRUE;
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default: IsLoad = FALSE;
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default: IsLoad = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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|
|
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function IsMov2Seg;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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`R2:
|
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if (isn[6])
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IsMov2Seg = isn[47:42]==`MOV2SEG;
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else
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case(isn[`INSTRUCTION_S2])
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`MOV2SEG: IsMov2Seg = TRUE;
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`RTI: IsMov2Seg = TRUE;
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default: IsMov2Seg = FALSE;
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endcase
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`RET:
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IsMov2Seg = TRUE;
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default: IsMov2Seg = FALSE;
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endcase
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endfunction
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function IsVolatileLoad;
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function IsVolatileLoad;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`R2:
|
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if (isn[6])
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IsVolatileLoad = isn[47:42]==`MOV2SEG;
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else
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IsVolatileLoad = isn[31:26]==`MOV2SEG;
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`MEMNDX:
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`MEMNDX:
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if (isn[`INSTRUCTION_L2]==2'b00)
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if (isn[`INSTRUCTION_L2]==2'b00)
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case({isn[31:28],isn[22:21]})
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case({isn[31:28],isn[22:21]})
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`LWRX: IsVolatileLoad = TRUE;
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`LWRX: IsVolatileLoad = TRUE;
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`LVBX: IsVolatileLoad = TRUE;
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`LVBX: IsVolatileLoad = TRUE;
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| Line 332... |
Line 360... |
`INC: IsStore = TRUE;
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`INC: IsStore = TRUE;
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default: IsStore = FALSE;
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default: IsStore = FALSE;
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endcase
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endcase
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else
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else
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IsStore = FALSE;
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IsStore = FALSE;
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`PUSHC: IsStore = TRUE;
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`SB: IsStore = TRUE;
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`SB: IsStore = TRUE;
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`Sx: IsStore = TRUE;
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`Sx: IsStore = TRUE;
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`SWC: IsStore = TRUE;
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`SWC: IsStore = TRUE;
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`INC: IsStore = TRUE;
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`INC: IsStore = TRUE;
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`SV: IsStore = TRUE;
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`SV: IsStore = TRUE;
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| Line 363... |
Line 392... |
`PUSH: IsPush = TRUE;
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`PUSH: IsPush = TRUE;
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default: IsPush = FALSE;
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default: IsPush = FALSE;
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endcase
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endcase
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else
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else
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IsPush = FALSE;
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IsPush = FALSE;
|
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`PUSHC: IsPush = TRUE;
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default: IsPush = FALSE;
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default: IsPush = FALSE;
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endcase
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endcase
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endfunction
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endfunction
|
|
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function [0:0] IsMem;
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function IsPushc;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`PUSHC: IsPushc = TRUE;
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default: IsPushc = FALSE;
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|
endcase
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endfunction
|
|
|
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//function [0:0] IsMem;
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reg IsMem;
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always @*
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//input [47:0] isn;
|
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case(instr[`INSTRUCTION_OP])
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`R2:
|
|
if (instr[6])
|
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IsMem = instr[47:42]==`MOV2SEG;
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|
else
|
|
case(instr[`INSTRUCTION_S2])
|
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`MOV2SEG: IsMem = TRUE;
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`RTI: IsMem = TRUE;
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default: IsMem = FALSE;
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endcase
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`MEMNDX: IsMem = TRUE;
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`MEMNDX: IsMem = TRUE;
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`AMO: IsMem = TRUE;
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`AMO: IsMem = TRUE;
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`LB: IsMem = TRUE;
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`LB: IsMem = TRUE;
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`LBU: IsMem = TRUE;
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`LBU: IsMem = TRUE;
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`Lx: IsMem = TRUE;
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`Lx: IsMem = TRUE;
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`LxU: IsMem = TRUE;
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`LxU: IsMem = TRUE;
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`LWR: IsMem = TRUE;
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`LWR: IsMem = TRUE;
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`LV,`SV: IsMem = TRUE;
|
`LV,`SV: IsMem = TRUE;
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`INC: IsMem = TRUE;
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`INC: IsMem = TRUE;
|
|
`PUSHC: IsMem = TRUE;
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`SB: IsMem = TRUE;
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`SB: IsMem = TRUE;
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`Sx: IsMem = TRUE;
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`Sx: IsMem = TRUE;
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`SWC: IsMem = TRUE;
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`SWC: IsMem = TRUE;
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`CAS: IsMem = TRUE;
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`CAS: IsMem = TRUE;
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`LVx: IsMem = TRUE;
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`LVx: IsMem = TRUE;
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`LVxU: IsMem = TRUE;
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`LVxU: IsMem = TRUE;
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//`RET: IsMem = TRUE;???
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default: IsMem = FALSE;
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default: IsMem = FALSE;
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endcase
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endcase
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endfunction
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//endfunction
|
|
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function IsMemNdx;
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function IsMemNdx;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`MEMNDX: IsMemNdx = TRUE;
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`MEMNDX: IsMemNdx = TRUE;
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| Line 439... |
Line 490... |
end
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end
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else
|
else
|
MemSize = octa;
|
MemSize = octa;
|
`LB,`LBU: MemSize = byt;
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`LB,`LBU: MemSize = byt;
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`Lx,`LxU,`LVx,`LVxU:
|
`Lx,`LxU,`LVx,`LVxU:
|
casez(isn[20:18])
|
casez(isn[21:18])
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3'b100: MemSize = octa;
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4'b1000: MemSize = hexi;
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3'b?10: MemSize = tetra;
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4'b?100: MemSize = octa;
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3'b??1: MemSize = wyde;
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4'b??10: MemSize = tetra;
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4'b???1: MemSize = wyde;
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default: MemSize = octa;
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default: MemSize = octa;
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endcase
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endcase
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`LWR: MemSize = octa;
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`LWR: MemSize = octa;
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`LV: MemSize = octa;
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`LV: MemSize = octa;
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`AMO:
|
`AMO:
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| Line 457... |
Line 509... |
3'd3: MemSize = octa;
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3'd3: MemSize = octa;
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default: MemSize = octa;
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default: MemSize = octa;
|
endcase
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endcase
|
`SB: MemSize = byt;
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`SB: MemSize = byt;
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`Sx:
|
`Sx:
|
casez(isn[15:13])
|
casez(isn[16:13])
|
3'b100: MemSize = octa;
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4'b1000: MemSize = hexi;
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3'b?10: MemSize = tetra;
|
4'b?100: MemSize = octa;
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3'b??1: MemSize = wyde;
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4'b??10: MemSize = tetra;
|
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4'b???1: MemSize = wyde;
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default: MemSize = octa;
|
default: MemSize = octa;
|
endcase
|
endcase
|
`SWC: MemSize = octa;
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`SWC: MemSize = octa;
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`SV: MemSize = octa;
|
`SV: MemSize = octa;
|
|
`PUSHC: MemSize = octa;
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default: MemSize = octa;
|
default: MemSize = octa;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsCAS;
|
function IsCAS;
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| Line 561... |
Line 615... |
IsShift = FALSE;
|
IsShift = FALSE;
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default: IsShift = FALSE;
|
default: IsShift = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsCmp;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`R2:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[31:26])
|
|
`CMP: IsCmp = TRUE;
|
|
default: IsCmp = FALSE;
|
|
endcase
|
|
else
|
|
IsCmp = FALSE;
|
|
`CMPI: IsCmp = TRUE;
|
|
default: IsCmp = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
function IsLWRX;
|
function IsLWRX;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| Line 619... |
Line 657... |
// Does not include BccR's
|
// Does not include BccR's
|
function IsBranch;
|
function IsBranch;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`Bcc: IsBranch = TRUE;
|
`Bcc: IsBranch = TRUE;
|
|
`BLcc: IsBranch = TRUE;
|
`BBc: IsBranch = TRUE;
|
`BBc: IsBranch = TRUE;
|
`BEQI: IsBranch = TRUE;
|
`BEQI: IsBranch = TRUE;
|
|
`BNEI: IsBranch = TRUE;
|
`CHK: IsBranch = TRUE;
|
`CHK: IsBranch = TRUE;
|
default: IsBranch = FALSE;
|
default: IsBranch = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
| Line 653... |
Line 693... |
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_S2]==`RTI;
|
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_S2]==`RTI;
|
endfunction
|
endfunction
|
|
|
function IsSync;
|
function IsSync;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC) || IsRti(isn);
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC) || IsRti(isn) || IsMov2Seg(isn);
|
endfunction
|
endfunction
|
|
|
// Has an extendable 14-bit constant
|
// Has an extendable 14-bit constant
|
function HasConst;
|
function HasConst;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`ADDI: HasConst = TRUE;
|
`ADDI: HasConst = TRUE;
|
|
`SEQI: HasConst = TRUE;
|
`SLTI: HasConst = TRUE;
|
`SLTI: HasConst = TRUE;
|
`SLTUI: HasConst = TRUE;
|
`SLTUI: HasConst = TRUE;
|
`SGTI: HasConst = TRUE;
|
`SGTI: HasConst = TRUE;
|
`SGTUI: HasConst = TRUE;
|
`SGTUI: HasConst = TRUE;
|
`ANDI: HasConst = TRUE;
|
`ANDI: HasConst = TRUE;
|
| Line 692... |
Line 733... |
`JAL: HasConst = TRUE;
|
`JAL: HasConst = TRUE;
|
`CALL: HasConst = TRUE;
|
`CALL: HasConst = TRUE;
|
`RET: HasConst = TRUE;
|
`RET: HasConst = TRUE;
|
`LVx: HasConst = TRUE;
|
`LVx: HasConst = TRUE;
|
`LVxU: HasConst = TRUE;
|
`LVxU: HasConst = TRUE;
|
|
`PUSHC: HasConst = TRUE;
|
default: HasConst = FALSE;
|
default: HasConst = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsOddball;
|
function IsOddball;
|
| Line 740... |
Line 782... |
`MEMDB,`MEMSB,`SYNC,`SETWB,5'h14,5'h15: IsRFW = FALSE;
|
`MEMDB,`MEMSB,`SYNC,`SETWB,5'h14,5'h15: IsRFW = FALSE;
|
default: IsRFW = TRUE;
|
default: IsRFW = TRUE;
|
endcase
|
endcase
|
`ADD: IsRFW = TRUE;
|
`ADD: IsRFW = TRUE;
|
`SUB: IsRFW = TRUE;
|
`SUB: IsRFW = TRUE;
|
|
`SEQ: IsRFW = TRUE;
|
`SLT: IsRFW = TRUE;
|
`SLT: IsRFW = TRUE;
|
`SLTU: IsRFW = TRUE;
|
`SLTU: IsRFW = TRUE;
|
`SLE: IsRFW = TRUE;
|
`SLE: IsRFW = TRUE;
|
`SLEU: IsRFW = TRUE;
|
`SLEU: IsRFW = TRUE;
|
`AND: IsRFW = TRUE;
|
`AND: IsRFW = TRUE;
|
| Line 837... |
Line 880... |
else
|
else
|
IsRFW = FALSE;
|
IsRFW = FALSE;
|
`BBc: IsRFW = FALSE;
|
`BBc: IsRFW = FALSE;
|
`BITFIELD: IsRFW = TRUE;
|
`BITFIELD: IsRFW = TRUE;
|
`ADDI: IsRFW = TRUE;
|
`ADDI: IsRFW = TRUE;
|
|
`SEQI: IsRFW = TRUE;
|
`SLTI: IsRFW = TRUE;
|
`SLTI: IsRFW = TRUE;
|
`SLTUI: IsRFW = TRUE;
|
`SLTUI: IsRFW = TRUE;
|
`SGTI: IsRFW = TRUE;
|
`SGTI: IsRFW = TRUE;
|
`SGTUI: IsRFW = TRUE;
|
`SGTUI: IsRFW = TRUE;
|
`ANDI: IsRFW = TRUE;
|
`ANDI: IsRFW = TRUE;
|
| Line 862... |
Line 906... |
`LxU: IsRFW = TRUE;
|
`LxU: IsRFW = TRUE;
|
`LWR: IsRFW = TRUE;
|
`LWR: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`LVxU: IsRFW = TRUE;
|
`LVxU: IsRFW = TRUE;
|
|
`PUSHC: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
`AUIPC: IsRFW = TRUE;
|
`AUIPC: IsRFW = TRUE;
|
`LUI: IsRFW = TRUE;
|
`LUI: IsRFW = TRUE;
|
| Line 880... |
Line 925... |
`R2:
|
`R2:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`CMP: fnWe = 8'h00; // CMP sets predicate registers so doesn't update general register file.
|
`CMP: fnWe = 8'h00; // CMP sets predicate registers so doesn't update general register file.
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
`CMPI: fnWe = 8'h00;
|
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
/*
|
/*
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`R2:
|
`R2:
|
| Line 930... |
Line 974... |
function Source1Valid;
|
function Source1Valid;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: Source1Valid = TRUE;
|
`BRK: Source1Valid = TRUE;
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
|
`BLcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
|
`BNEI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
endcase
|
endcase
|
`MEMNDX: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`MEMNDX: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
|
`SEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| Line 962... |
Line 1009... |
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
|
`PUSHC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| Line 982... |
Line 1030... |
function Source2Valid;
|
function Source2Valid;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: Source2Valid = TRUE;
|
`BRK: Source2Valid = TRUE;
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
|
`BLcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`BBc: Source2Valid = TRUE;
|
`BBc: Source2Valid = TRUE;
|
`BEQI: Source2Valid = TRUE;
|
`BEQI: Source2Valid = TRUE;
|
|
`BNEI: Source2Valid = TRUE;
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R1: Source2Valid = TRUE;
|
`R1: Source2Valid = TRUE;
|
`SHIFTR: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT31: Source2Valid = TRUE;
|
`SHIFT31: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT63: Source2Valid = TRUE;
|
`SHIFT63: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
endcase
|
endcase
|
`MEMNDX:
|
`MEMNDX:
|
if (IsLoad(isn))
|
if (IsLoad(isn))
|
case({isn[31:28],isn[22:21]})
|
case({isn[31:28],isn[22:21]})
|
| Line 1004... |
Line 1053... |
case({isn[31:28],isn[17:16]})
|
case({isn[31:28],isn[17:16]})
|
`SVX: Source2Valid = FALSE;
|
`SVX: Source2Valid = FALSE;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
endcase
|
endcase
|
`ADDI: Source2Valid = TRUE;
|
`ADDI: Source2Valid = TRUE;
|
|
`SEQI: Source2Valid = TRUE;
|
`SLTI: Source2Valid = TRUE;
|
`SLTI: Source2Valid = TRUE;
|
`SLTUI: Source2Valid = TRUE;
|
`SLTUI: Source2Valid = TRUE;
|
`SGTI: Source2Valid = TRUE;
|
`SGTI: Source2Valid = TRUE;
|
`SGTUI: Source2Valid = TRUE;
|
`SGTUI: Source2Valid = TRUE;
|
`ANDI: Source2Valid = TRUE;
|
`ANDI: Source2Valid = TRUE;
|
| Line 1023... |
Line 1073... |
`LVx: Source2Valid = TRUE;
|
`LVx: Source2Valid = TRUE;
|
`INC: Source2Valid = TRUE;
|
`INC: Source2Valid = TRUE;
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
|
`PUSHC: Source2Valid = TRUE;
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`JAL: Source2Valid = TRUE;
|
`JAL: Source2Valid = TRUE;
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
| Line 1094... |
Line 1145... |
`else
|
`else
|
always @*
|
always @*
|
`endif
|
`endif
|
begin
|
begin
|
bus <= 144'h0;
|
bus <= 144'h0;
|
bus[`IB_CMP] <= IsCmp(instr);
|
bus[`IB_LOADSEG] <= IsMov2Seg(instr);
|
if (IsStore(instr))
|
bus[`IB_CMP] <= 1'b0;//IsCmp(instr);
|
|
if (IsStore(instr) & !IsPushc(instr))
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:23],instr[17:13]} :
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:23],instr[17:13]} :
|
{{50{instr[31]}},instr[31:23],instr[17:13]};
|
{{50{instr[31]}},instr[31:23],instr[17:13]};
|
else
|
else
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
|
{{50{instr[31]}},instr[31:18]};
|
{{50{instr[31]}},instr[31:18]};
|
| Line 1141... |
Line 1193... |
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
bus[`IB_STORE] <= IsStore(instr);
|
bus[`IB_STORE] <= IsStore(instr);
|
bus[`IB_PUSH] <= IsPush(instr);
|
bus[`IB_PUSH] <= IsPush(instr);
|
bus[`IB_ODDBALL] <= IsOddball(instr);
|
bus[`IB_ODDBALL] <= IsOddball(instr);
|
bus[`IB_MEMSZ] <= MemSize(instr);
|
bus[`IB_MEMSZ] <= MemSize(instr);
|
bus[`IB_MEM] <= IsMem(instr);
|
bus[`IB_MEM] <= IsMem;
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
bus[`IB_SHFT] <= IsShift48(instr);//|IsShift(instr);
|
bus[`IB_SHFT] <= IsShift48(instr);//|IsShift(instr);
|
| Line 1155... |
Line 1207... |
bus[`IB_JMP] <= IsJmp(instr);
|
bus[`IB_JMP] <= IsJmp(instr);
|
bus[`IB_BR] <= IsBranch(instr);
|
bus[`IB_BR] <= IsBranch(instr);
|
bus[`IB_SYNC] <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
|
bus[`IB_SYNC] <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
|
bus[`IB_FSYNC] <= IsFSync(instr);
|
bus[`IB_FSYNC] <= IsFSync(instr);
|
bus[`IB_RFW] <= (Rt==5'd0) ? 1'b0 : IsRFW(instr);// && !IsCmp(instr);
|
bus[`IB_RFW] <= (Rt==5'd0) ? 1'b0 : IsRFW(instr);// && !IsCmp(instr);
|
bus[`IB_PRFW] <= IsCmp(instr);
|
bus[`IB_PRFW] <= 1'b0;//IsCmp(instr);
|
bus[`IB_WE] <= fnWe(instr);
|
bus[`IB_WE] <= fnWe(instr);
|
id_o <= id_i;
|
id_o <= id_i;
|
idv_o <= idv_i;
|
idv_o <= idv_i;
|
end
|
end
|
|
|
| Line 1182... |
Line 1234... |
endcase
|
endcase
|
else
|
else
|
IsALU = TRUE;
|
IsALU = TRUE;
|
`BRK: IsALU = FALSE;
|
`BRK: IsALU = FALSE;
|
`Bcc: IsALU = FALSE;
|
`Bcc: IsALU = FALSE;
|
|
`BLcc: IsALU = FALSE;
|
`BBc: IsALU = FALSE;
|
`BBc: IsALU = FALSE;
|
`BEQI: IsALU = FALSE;
|
`BEQI: IsALU = FALSE;
|
|
`BNEI: IsALU = FALSE;
|
`CHK: IsALU = FALSE;
|
`CHK: IsALU = FALSE;
|
`JAL: IsALU = FALSE;
|
`JAL: IsALU = FALSE;
|
`JMP: IsALU = FALSE;
|
`JMP: IsALU = FALSE;
|
`CALL: IsALU = FALSE;
|
`CALL: IsALU = FALSE;
|
`RET: IsALU = FALSE;
|
`RET: IsALU = FALSE;
|
