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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_ipt.v] - Diff between revs 60 and 61

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Line 1... Line 1... 
// ============================================================================
 
// ============================================================================
 
//        __
 
//        __
 
//   \\__/ o\    (C) 2018  Robert Finch, Waterloo
 
//   \\__/ o\    (C) 2018-2019  Robert Finch, Waterloo
 
//    \  __ /    All rights reserved.
 
//    \  __ /    All rights reserved.
 
//     \/_//     robfinch<remove>@finitron.ca
 
//     \/_//     robfinch<remove>@finitron.ca
 
//       ||
 
//       ||
 
//
 
//
 
//      FT64_ipt.v
 
//      FT64_ipt.v
Line 25... Line 25... 
//
 
//
 
`ifndef TRUE
 
`ifndef TRUE
 
`define TRUE    1'b1
 
`define TRUE    1'b1
 
`define FALSE   1'b0
 
`define FALSE   1'b0
 
`endif
 
`endif
 
 
 
//`define BYPASS        1'b1
 
 
 
 
 
module FT64_ipt(rst, clk, pkeys_i, ol_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,
 
module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,
 
        cyc_o, ack_i, we_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);
 
        bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);
 
input rst;
 
input rst;
 
input clk;
 
input clk;
 
input [63:0] pkeys_i;
 
input [63:0] pkeys_i;
 
input [1:0] ol_i;
 
input [1:0] ol_i;
 
 
 
input [1:0] bte_i;
 
input [2:0] cti_i;
 
input [2:0] cti_i;
 
input cs_i;
 
input cs_i;
 
input icl_i;
 
input icl_i;
 
input cyc_i;
 
input cyc_i;
 
input stb_i;
 
input stb_i;
Line 43... Line 45... 
input we_i;
 
input we_i;
 
input [7:0] sel_i;
 
input [7:0] sel_i;
 
input [63:0] vadr_i;
 
input [63:0] vadr_i;
 
input [63:0] dat_i;
 
input [63:0] dat_i;
 
output reg [63:0] dat_o;
 
output reg [63:0] dat_o;
 
 
 
output reg [1:0] bte_o;
 
 
 
output reg [2:0] cti_o;
 
output reg cyc_o;
 
output reg cyc_o;
 
input ack_i;
 
input ack_i;
 
output reg we_o;
 
output reg we_o;
 
 
 
output reg [7:0] sel_o;
 
output reg [31:0] padr_o;
 
output reg [31:0] padr_o;
 
output reg exv_o;
 
output reg exv_o;
 
output reg rdv_o;
 
output reg rdv_o;
 
output reg wrv_o;
 
output reg wrv_o;
 
output reg prv_o;
 
output reg prv_o;
Line 62... Line 67... 
parameter S_CMP4 = 4'd4;
 
parameter S_CMP4 = 4'd4;
 
parameter S_CMP5 = 4'd5;
 
parameter S_CMP5 = 4'd5;
 
parameter S_CMP6 = 4'd6;
 
parameter S_CMP6 = 4'd6;
 
parameter S_WAIT1 = 4'd7;
 
parameter S_WAIT1 = 4'd7;
 
parameter S_ACK = 4'd8;
 
parameter S_ACK = 4'd8;
 
 
 
parameter S_RESET = 4'd9;
 
 
 
 
 
integer n;
 
integer n;
 
wire [9:0] pkey [0:5];
 
wire [9:0] pkey [0:5];
 
assign pkey[0] = pkeys_i[9:0];
 
assign pkey[0] = pkeys_i[9:0];
 
assign pkey[1] = pkeys_i[19:10];
 
assign pkey[1] = pkeys_i[19:10];
Line 103... Line 109... 
wire [9:0] pt_key = pt_dat[41:32];
 
wire [9:0] pt_key = pt_dat[41:32];
 
 
 
 
 
reg keymatch;
 
reg keymatch;
 
always @*
 
always @*
 
begin
 
begin
 
keymatch = 1'b0;
 
keymatch = ol_i==2'b00;
 
for (n = 0; n < 6; n = n + 1)
 
for (n = 0; n < 6; n = n + 1)
 
        if (pt_key==pkey[n] || pt_key==10'h0)
 
        if (pt_key==pkey[n] || pt_key==10'h0)
 
                keymatch = 1'b1;
 
                keymatch = 1'b1;
 
end
 
end
 
 
 
 
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                dat_o <= pte_vadr;
 
                dat_o <= pte_vadr;
 
        default:        dat_o <= 1'b0;
 
        default:        dat_o <= 1'b0;
 
        endcase
 
        endcase
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
 
 
        bte_o <= bte_i;
 
 
 
always @(posedge clk)
 
 
 
        cti_o <= cti_i;
 
 
 
always @(posedge clk)
 
 
 
        sel_o <= sel_i;
 
 
 
`ifdef BYPASS
 
 
 
always @(posedge clk)
 
 
 
        cyc_o <= cyc_i;
 
 
 
always @(posedge clk)
 
 
 
        we_o <= we_i;
 
 
 
always @(posedge clk)
 
 
 
        padr_o <= vadr_i[31:0];
 
 
 
always @(posedge clk)
 
 
 
        exv_o <= 1'b0;
 
 
 
always @(posedge clk)
 
 
 
        rdv_o <= 1'b0;
 
 
 
always @(posedge clk)
 
 
 
        wrv_o <= 1'b0;
 
 
 
always @(posedge clk)
 
 
 
        prv_o <= 1'b0;
 
 
 
always @(posedge clk)
 
 
 
        page_fault <= 1'b0;
 
 
 
`else
 
 
 
always @(posedge clk)
 
if (rst) begin
 
if (rst) begin
 
        cyc_o <= 1'b0;
 
        cyc_o <= 1'b0;
 
        padr_o <= 32'hFFFC0100;
 
        padr_o <= 32'hFFFC0100;
 
        ack_o <= 1'b0;
 
        ack_o <= 1'b0;
 
        exv_o <= 1'b0;
 
        exv_o <= 1'b0;
 
        rdv_o <= 1'b0;
 
        rdv_o <= 1'b0;
 
        wrv_o <= 1'b0;
 
        wrv_o <= 1'b0;
 
        prv_o <= 1'b0;
 
        prv_o <= 1'b0;
 
        pt_wr <= 1'b0;
 
        pt_wr <= 1'b1;
 
 
 
        pt_ad <= 1'b0;
 
 
 
        pt_dati <= 1'b0;
 
        upd <= 1'b0;
 
        upd <= 1'b0;
 
        probe <= 1'b0;
 
        probe <= 1'b0;
 
        upd_done <= 1'b0;
 
        upd_done <= 1'b0;
 
        probe_done <= 1'b0;
 
        probe_done <= 1'b0;
 
        goto(S_IDLE);
 
        goto(S_IDLE);
Line 161... Line 193... 
else begin
 
else begin
 
        pt_wr <= 1'b0;
 
        pt_wr <= 1'b0;
 
        page_fault <= 1'b0;
 
        page_fault <= 1'b0;
 
        ack_o <= 1'b0;
 
        ack_o <= 1'b0;
 
case(state)
 
case(state)
 
 
 
// Clear page table ram on reset.
 
 
 
S_RESET:
 
 
 
        begin
 
 
 
                pt_ad <= pt_ad + 2'd1;
 
 
 
                if (&pt_ad) begin
 
 
 
                        pt_wr <= 1'b0;
 
 
 
                        state <= S_IDLE;
 
 
 
                end
 
 
 
        end
 
S_IDLE:
 
S_IDLE:
 
        if (cyc_i) begin
 
        if (cyc_i) begin
 
                if (cs_i) begin
 
                if (cs_i & stb_i) begin
 
                        ack_o <= 1'b1;
 
                        ack_o <= 1'b1;
 
                        case(vadr_i[5:3])
 
                        case(vadr_i[5:3])
 
                        3'd0:
 
                        3'd0:
 
                                begin
 
                                begin
 
                                        if (dat_i[0] & !upd_done) begin
 
                                        if (dat_i[0] & !upd_done) begin
Line 200... Line 241... 
                        upd <= 1'b0;
 
                        upd <= 1'b0;
 
                        probe <= 1'b0;
 
                        probe <= 1'b0;
 
                        if (ol_i==2'b0) begin
 
                        if (ol_i==2'b0) begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                we_o <= we_i;
 
                                we_o <= we_i;
 
                                padr_o <= vadr_i;
 
                                padr_o <= vadr_i[31:0];
 
                                goto(S_ACK);
 
                                goto(S_ACK);
 
                        end
 
                        end
 
                        else begin
 
                        else begin
 
                                // Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are
 
                                // Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are
 
                                // not mapped.
 
                                // not mapped.
 
                                if (vadr_i[31:24]==8'hFF || vadr_i[31:24]==8'h00) begin
 
                                if (vadr_i[31:24]==8'hFF || vadr_i[31:24]==8'h00) begin
 
                                        cyc_o <= 1'b1;
 
                                        cyc_o <= 1'b1;
 
                                        we_o <= we_i;
 
                                        we_o <= we_i;
 
                                        padr_o <= vadr_i;
 
                                        padr_o <= vadr_i[31:0];
 
                                        goto(S_ACK);
 
                                        goto(S_ACK);
 
                                end
 
                                end
 
                                else begin
 
                                else begin
 
                                        pt_ad <= Hash1({vadr_i[63:56],vadr_i});
 
                                        pt_ad <= Hash1({vadr_i[63:56],vadr_i});
 
                                        goto(S_CMP1);
 
                                        goto(S_CMP1);
Line 292... Line 333... 
                                padr_o <= {pt_ad,vadr_i[12:0]};
 
                                padr_o <= {pt_ad,vadr_i[12:0]};
 
                        end
 
                        end
 
                        else begin
 
                        else begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                we_o <= 1'b0;
 
                                we_o <= 1'b0;
 
                                padr_o <= 64'hFFFFFFFFFFFFFFF8;
 
                                padr_o <= 32'hFFFFFFF8;
 
                                prv_o <= 1'b1;
 
                                prv_o <= 1'b1;
 
                        end
 
                        end
 
                        goto(S_ACK);
 
                        goto(S_ACK);
 
                end
 
                end
 
        end
 
        end
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                                padr_o <= {pt_ad,vadr_i[12:0]};
 
                                padr_o <= {pt_ad,vadr_i[12:0]};
 
                        end
 
                        end
 
                        else begin
 
                        else begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                we_o <= 1'b0;
 
                                we_o <= 1'b0;
 
                                padr_o <= 64'hFFFFFFFFFFFFFFF8;
 
                                padr_o <= 32'hFFFFFFF8;
 
                                prv_o <= 1'b1;
 
                                prv_o <= 1'b1;
 
                        end
 
                        end
 
                        goto(S_ACK);
 
                        goto(S_ACK);
 
                end
 
                end
 
        end
 
        end
Line 398... Line 439... 
                end
 
                end
 
        end
 
        end
 
 
 
 
 
endcase
 
endcase
 
end
 
end
 
 
 
`endif
 
 
 
 
 
task goto;
 
task goto;
 
input [3:0] nst;
 
input [3:0] nst;
 
begin
 
begin
 
        state <= nst;
 
        state <= nst;

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