// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_ipt.v
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// FT64_ipt.v
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// - 64 bit CPU inverted page table memory management unit
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// - 64 bit CPU inverted page table memory management unit
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`ifndef TRUE
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`ifndef TRUE
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`define TRUE 1'b1
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`define TRUE 1'b1
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`define FALSE 1'b0
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`define FALSE 1'b0
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`endif
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`endif
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//`define BYPASS 1'b1
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`define BYPASS 1'b1
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module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,
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module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,
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bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);
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bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);
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input rst;
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input rst;
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input clk;
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input clk;
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input [63:0] pkeys_i;
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input [63:0] pkeys_i;
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input [1:0] ol_i;
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input [1:0] ol_i;
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input [1:0] bte_i;
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input [1:0] bte_i;
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input [2:0] cti_i;
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input [2:0] cti_i;
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input cs_i;
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input cs_i;
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input icl_i;
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input icl_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output reg ack_o;
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output reg ack_o;
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input we_i;
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input we_i;
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input [7:0] sel_i;
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input [7:0] sel_i;
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input [63:0] vadr_i;
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input [63:0] vadr_i;
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input [63:0] dat_i;
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input [63:0] dat_i;
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output reg [63:0] dat_o;
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output reg [63:0] dat_o;
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output reg [1:0] bte_o;
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output reg [1:0] bte_o;
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output reg [2:0] cti_o;
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output reg [2:0] cti_o;
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output reg cyc_o;
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output reg cyc_o;
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input ack_i;
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input ack_i;
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output reg we_o;
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output reg we_o;
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output reg [7:0] sel_o;
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output reg [7:0] sel_o;
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output reg [31:0] padr_o;
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output reg [31:0] padr_o;
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output reg exv_o;
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output reg exv_o;
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output reg rdv_o;
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output reg rdv_o;
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output reg wrv_o;
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output reg wrv_o;
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output reg prv_o;
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output reg prv_o;
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output reg page_fault;
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output reg page_fault;
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parameter S_IDLE = 4'd0;
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parameter S_IDLE = 4'd0;
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parameter S_CMP1 = 4'd1;
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parameter S_CMP1 = 4'd1;
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parameter S_CMP2 = 4'd2;
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parameter S_CMP2 = 4'd2;
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parameter S_CMP3 = 4'd3;
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parameter S_CMP3 = 4'd3;
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parameter S_CMP4 = 4'd4;
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parameter S_CMP4 = 4'd4;
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parameter S_CMP5 = 4'd5;
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parameter S_CMP5 = 4'd5;
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parameter S_CMP6 = 4'd6;
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parameter S_CMP6 = 4'd6;
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parameter S_WAIT1 = 4'd7;
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parameter S_WAIT1 = 4'd7;
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parameter S_ACK = 4'd8;
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parameter S_ACK = 4'd8;
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parameter S_RESET = 4'd9;
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parameter S_RESET = 4'd9;
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integer n;
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integer n;
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wire [9:0] pkey [0:5];
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wire [9:0] pkey [0:5];
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assign pkey[0] = pkeys_i[9:0];
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assign pkey[0] = pkeys_i[9:0];
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assign pkey[1] = pkeys_i[19:10];
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assign pkey[1] = pkeys_i[19:10];
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assign pkey[2] = pkeys_i[29:20];
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assign pkey[2] = pkeys_i[29:20];
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assign pkey[3] = pkeys_i[39:30];
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assign pkey[3] = pkeys_i[39:30];
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assign pkey[4] = pkeys_i[49:40];
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assign pkey[4] = pkeys_i[49:40];
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assign pkey[5] = pkeys_i[59:50];
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assign pkey[5] = pkeys_i[59:50];
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reg [3:0] state;
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reg [3:0] state;
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reg [15:0] pt_ad;
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reg [15:0] pt_ad;
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reg upd;
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reg upd;
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reg upd_done;
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reg upd_done;
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reg probe, probe_done;
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reg probe, probe_done;
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reg pte_last;
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reg pte_last;
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reg [7:0] pte_asid;
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reg [7:0] pte_asid;
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reg [3:0] pte_drwx;
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reg [3:0] pte_drwx;
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reg [18:0] pte_vadr;
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reg [18:0] pte_vadr;
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reg [9:0] pte_key;
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reg [9:0] pte_key;
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reg pt_wr;
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reg pt_wr;
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reg [41:0] pt_dati;
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reg [41:0] pt_dati;
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wire [41:0] pt_dat;
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wire [41:0] pt_dat;
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FT64_iptram uram1 (
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FT64_iptram uram1 (
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.clka(clk),
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.clka(clk),
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.ena(1'b1),
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.ena(1'b1),
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.wea(pt_wr),
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.wea(pt_wr),
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.addra(pt_ad),
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.addra(pt_ad),
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.dina(pt_dati),
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.dina(pt_dati),
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.douta(pt_dat)
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.douta(pt_dat)
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);
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);
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wire pt_last = pt_dat[23];
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wire pt_last = pt_dat[23];
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wire [18:0] pt_vadr = pt_dat[22:4];
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wire [18:0] pt_vadr = pt_dat[22:4];
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wire [7:0] pt_asid = pt_dat[31:24];
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wire [7:0] pt_asid = pt_dat[31:24];
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wire [3:0] pt_drwx = pt_dat[3:0];
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wire [3:0] pt_drwx = pt_dat[3:0];
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wire [9:0] pt_key = pt_dat[41:32];
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wire [9:0] pt_key = pt_dat[41:32];
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reg keymatch;
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reg keymatch;
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always @*
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always @*
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begin
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begin
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keymatch = ol_i==2'b00;
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keymatch = ol_i==2'b00;
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for (n = 0; n < 6; n = n + 1)
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for (n = 0; n < 6; n = n + 1)
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if (pt_key==pkey[n] || pt_key==10'h0)
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if (pt_key==pkey[n] || pt_key==10'h0)
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keymatch = 1'b1;
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keymatch = 1'b1;
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end
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end
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function [15:0] Hash1;
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function [15:0] Hash1;
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input [39:0] vadr;
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input [39:0] vadr;
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begin
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begin
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Hash1 = {1'b0,vadr[37:32],vadr[21:13]};
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Hash1 = {1'b0,vadr[37:32],vadr[21:13]};
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end
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end
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endfunction
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endfunction
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function [15:0] Hash2;
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function [15:0] Hash2;
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input [39:0] vadr;
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input [39:0] vadr;
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begin
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begin
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Hash2 = {1'b1,vadr[37:32],vadr[21:13]};
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Hash2 = {1'b1,vadr[37:32],vadr[21:13]};
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end
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end
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endfunction
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endfunction
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always @(posedge clk)
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always @(posedge clk)
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case(vadr_i[5:3])
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case(vadr_i[5:3])
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3'd1:
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3'd1:
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dat_o <= pt_ad;
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dat_o <= pt_ad;
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3'd2:
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3'd2:
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begin
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begin
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dat_o[41:32] <= pte_key;
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dat_o[41:32] <= pte_key;
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dat_o[31:24] <= pte_asid;
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dat_o[31:24] <= pte_asid;
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dat_o[23] <= pte_last;
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dat_o[23] <= pte_last;
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dat_o[2:0] <= pte_drwx[2:0];
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dat_o[2:0] <= pte_drwx[2:0];
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dat_o[7] <= pte_drwx[3];
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dat_o[7] <= pte_drwx[3];
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end
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end
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3'd3:
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3'd3:
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dat_o <= pte_vadr;
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dat_o <= pte_vadr;
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default: dat_o <= 1'b0;
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default: dat_o <= 1'b0;
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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bte_o <= bte_i;
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bte_o <= bte_i;
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always @(posedge clk)
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always @(posedge clk)
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cti_o <= cti_i;
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cti_o <= cti_i;
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always @(posedge clk)
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always @(posedge clk)
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sel_o <= sel_i;
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sel_o <= sel_i;
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`ifdef BYPASS
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`ifdef BYPASS
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always @(posedge clk)
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always @(posedge clk)
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pt_wr <= 1'b0;
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always @(posedge clk)
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pt_ad <= 16'h0;
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always @(posedge clk)
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pt_dati <= 42'h0;
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always @(posedge clk)
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cyc_o <= cyc_i;
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cyc_o <= cyc_i;
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always @(posedge clk)
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always @(posedge clk)
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we_o <= we_i;
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we_o <= we_i;
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always @(posedge clk)
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always @(posedge clk)
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padr_o <= vadr_i[31:0];
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padr_o <= vadr_i[31:0];
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always @(posedge clk)
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always @(posedge clk)
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exv_o <= 1'b0;
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exv_o <= 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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rdv_o <= 1'b0;
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rdv_o <= 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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wrv_o <= 1'b0;
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wrv_o <= 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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prv_o <= 1'b0;
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prv_o <= 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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page_fault <= 1'b0;
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page_fault <= 1'b0;
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always @(posedge clk)
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ack_o <= 1'b0;
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`else
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`else
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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padr_o <= 32'hFFFC0100;
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padr_o <= 32'hFFFC0100;
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ack_o <= 1'b0;
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ack_o <= 1'b0;
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exv_o <= 1'b0;
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exv_o <= 1'b0;
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rdv_o <= 1'b0;
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rdv_o <= 1'b0;
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wrv_o <= 1'b0;
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wrv_o <= 1'b0;
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prv_o <= 1'b0;
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prv_o <= 1'b0;
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pt_wr <= 1'b1;
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pt_wr <= 1'b1;
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pt_ad <= 1'b0;
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pt_ad <= 1'b0;
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pt_dati <= 1'b0;
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pt_dati <= 1'b0;
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upd <= 1'b0;
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upd <= 1'b0;
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probe <= 1'b0;
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probe <= 1'b0;
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upd_done <= 1'b0;
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upd_done <= 1'b0;
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probe_done <= 1'b0;
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probe_done <= 1'b0;
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goto(S_IDLE);
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goto(S_IDLE);
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end
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end
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else begin
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else begin
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pt_wr <= 1'b0;
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pt_wr <= 1'b0;
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page_fault <= 1'b0;
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page_fault <= 1'b0;
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ack_o <= 1'b0;
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ack_o <= 1'b0;
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case(state)
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case(state)
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// Clear page table ram on reset.
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// Clear page table ram on reset.
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S_RESET:
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S_RESET:
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begin
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begin
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pt_ad <= pt_ad + 2'd1;
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pt_ad <= pt_ad + 2'd1;
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if (&pt_ad) begin
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if (&pt_ad) begin
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pt_wr <= 1'b0;
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pt_wr <= 1'b0;
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state <= S_IDLE;
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state <= S_IDLE;
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end
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end
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end
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end
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S_IDLE:
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S_IDLE:
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if (cyc_i) begin
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if (cyc_i) begin
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if (cs_i & stb_i) begin
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if (cs_i & stb_i) begin
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ack_o <= 1'b1;
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ack_o <= 1'b1;
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case(vadr_i[5:3])
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case(vadr_i[5:3])
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3'd0:
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3'd0:
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begin
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begin
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if (dat_i[0] & !upd_done) begin
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if (dat_i[0] & !upd_done) begin
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pt_ad <= Hash1({pte_asid,pte_vadr});
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pt_ad <= Hash1({pte_asid,pte_vadr});
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upd <= 1'b1;
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upd <= 1'b1;
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goto(S_CMP1);
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goto(S_CMP1);
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end
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end
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else if (dat_i[1] & !probe_done) begin
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else if (dat_i[1] & !probe_done) begin
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pt_ad <= Hash1({pte_asid,pte_vadr});
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pt_ad <= Hash1({pte_asid,pte_vadr});
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probe <= 1'b1;
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probe <= 1'b1;
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goto(S_CMP1);
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goto(S_CMP1);
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end
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end
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end
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end
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3'd2:
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3'd2:
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begin
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begin
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pte_key <= dat_i[41:32];
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pte_key <= dat_i[41:32];
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pte_asid <= dat_i[31:24];
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pte_asid <= dat_i[31:24];
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pte_last <= dat_i[22];
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pte_last <= dat_i[22];
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pte_drwx <= {dat_i[7],dat_i[2:0]};
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pte_drwx <= {dat_i[7],dat_i[2:0]};
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end
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end
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3'd3:
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3'd3:
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begin
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begin
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pte_vadr <= dat_i[18:0];
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pte_vadr <= dat_i[18:0];
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end
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end
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endcase
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endcase
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end
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end
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else begin
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else begin
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upd_done <= 1'b0;
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upd_done <= 1'b0;
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probe_done <= 1'b0;
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probe_done <= 1'b0;
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upd <= 1'b0;
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upd <= 1'b0;
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probe <= 1'b0;
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probe <= 1'b0;
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if (ol_i==2'b0) begin
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if (ol_i==2'b0) begin
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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we_o <= we_i;
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we_o <= we_i;
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padr_o <= vadr_i[31:0];
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padr_o <= vadr_i[31:0];
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goto(S_ACK);
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goto(S_ACK);
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end
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end
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else begin
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else begin
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// Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are
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// Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are
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// not mapped.
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// not mapped.
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if (vadr_i[31:24]==8'hFF || vadr_i[31:24]==8'h00) begin
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if (vadr_i[31:24]==8'hFF || vadr_i[31:24]==8'h00) begin
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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we_o <= we_i;
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we_o <= we_i;
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padr_o <= vadr_i[31:0];
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padr_o <= vadr_i[31:0];
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goto(S_ACK);
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goto(S_ACK);
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end
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end
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else begin
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else begin
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pt_ad <= Hash1({vadr_i[63:56],vadr_i});
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pt_ad <= Hash1({vadr_i[63:56],vadr_i});
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goto(S_CMP1);
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goto(S_CMP1);
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end
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end
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end
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end
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end
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end
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end
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end
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else begin
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else begin
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exv_o <= 1'b0;
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exv_o <= 1'b0;
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rdv_o <= 1'b0;
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rdv_o <= 1'b0;
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wrv_o <= 1'b0;
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wrv_o <= 1'b0;
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prv_o <= 1'b0;
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prv_o <= 1'b0;
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end
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end
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S_CMP1:
|
S_CMP1:
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goto(S_CMP2);
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goto(S_CMP2);
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S_CMP2:
|
S_CMP2:
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goto(S_CMP3);
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goto(S_CMP3);
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S_CMP3:
|
S_CMP3:
|
if (pt_drwx[2:0]==3'b0) begin
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if (pt_drwx[2:0]==3'b0) begin
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if (upd) begin
|
if (upd) begin
|
pte_key <= 10'h0;
|
pte_key <= 10'h0;
|
pte_last <= 1'b0;
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pte_last <= 1'b0;
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pte_drwx <= 4'd0;
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pte_drwx <= 4'd0;
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pt_wr <= 1'b1;
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pt_wr <= 1'b1;
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pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
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pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
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upd_done <= 1'b1;
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upd_done <= 1'b1;
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goto(S_IDLE);
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goto(S_IDLE);
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end
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end
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else if (probe) begin
|
else if (probe) begin
|
pte_drwx <= 3'b0;
|
pte_drwx <= 3'b0;
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pte_vadr <= 19'b0;
|
pte_vadr <= 19'b0;
|
pte_asid <= 8'b0;
|
pte_asid <= 8'b0;
|
pte_last <= 1'b0;
|
pte_last <= 1'b0;
|
pte_key <= 10'h0;
|
pte_key <= 10'h0;
|
probe_done <= 1'b1;
|
probe_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else begin
|
else begin
|
page_fault <= 1'b1;
|
page_fault <= 1'b1;
|
goto(S_WAIT1);
|
goto(S_WAIT1);
|
end
|
end
|
end
|
end
|
else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
|
else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
|
if (upd) begin
|
if (upd) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
pte_key <= pt_key;
|
pte_key <= pt_key;
|
pte_last <= pt_last;
|
pte_last <= pt_last;
|
pte_drwx <= pt_drwx;
|
pte_drwx <= pt_drwx;
|
pt_wr <= 1'b1;
|
pt_wr <= 1'b1;
|
pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
|
pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
|
end
|
end
|
else
|
else
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
upd_done <= 1'b1;
|
upd_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else if (probe) begin
|
else if (probe) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
pte_key <= pt_key;
|
pte_key <= pt_key;
|
pte_last <= pt_last;
|
pte_last <= pt_last;
|
pte_drwx <= pt_drwx;
|
pte_drwx <= pt_drwx;
|
end
|
end
|
else
|
else
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
probe_done <= 1'b1;
|
probe_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else if (~ack_i) begin
|
else if (~ack_i) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
we_o <= we_i & pt_drwx[1];
|
we_o <= we_i & pt_drwx[1];
|
if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
|
if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
|
if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
|
if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
|
if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
|
if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
|
padr_o <= {pt_ad,vadr_i[12:0]};
|
padr_o <= {pt_ad,vadr_i[12:0]};
|
end
|
end
|
else begin
|
else begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
padr_o <= 32'hFFFFFFF8;
|
padr_o <= 32'hFFFFFFF8;
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
end
|
end
|
goto(S_ACK);
|
goto(S_ACK);
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (upd|probe)
|
if (upd|probe)
|
pt_ad <= Hash2({pte_asid,pte_vadr});
|
pt_ad <= Hash2({pte_asid,pte_vadr});
|
else
|
else
|
pt_ad <= Hash2({vadr_i[63:56],vadr_i});
|
pt_ad <= Hash2({vadr_i[63:56],vadr_i});
|
goto(S_CMP4);
|
goto(S_CMP4);
|
end
|
end
|
|
|
S_CMP4:
|
S_CMP4:
|
goto(S_CMP5);
|
goto(S_CMP5);
|
S_CMP5:
|
S_CMP5:
|
goto(S_CMP6);
|
goto(S_CMP6);
|
S_CMP6:
|
S_CMP6:
|
if (pt_drwx[2:0]==3'b0) begin
|
if (pt_drwx[2:0]==3'b0) begin
|
if (upd) begin
|
if (upd) begin
|
pte_key <= 10'h0;
|
pte_key <= 10'h0;
|
pte_last <= 1'b0;
|
pte_last <= 1'b0;
|
pte_drwx <= 4'd0;
|
pte_drwx <= 4'd0;
|
pt_wr <= 1'b1;
|
pt_wr <= 1'b1;
|
pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
|
pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
|
upd_done <= 1'b1;
|
upd_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else if (probe) begin
|
else if (probe) begin
|
pte_key <= 10'h0;
|
pte_key <= 10'h0;
|
pte_drwx <= 43'b0;
|
pte_drwx <= 43'b0;
|
pte_vadr <= 19'b0;
|
pte_vadr <= 19'b0;
|
pte_asid <= 8'b0;
|
pte_asid <= 8'b0;
|
pte_last <= 1'b0;
|
pte_last <= 1'b0;
|
probe_done <= 1'b1;
|
probe_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else begin
|
else begin
|
page_fault <= 1'b1;
|
page_fault <= 1'b1;
|
goto(S_WAIT1);
|
goto(S_WAIT1);
|
end
|
end
|
end
|
end
|
else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
|
else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
|
if (upd) begin
|
if (upd) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
pte_key <= pt_key;
|
pte_key <= pt_key;
|
pte_last <= pt_last;
|
pte_last <= pt_last;
|
pte_drwx <= pt_drwx;
|
pte_drwx <= pt_drwx;
|
pt_wr <= 1'b1;
|
pt_wr <= 1'b1;
|
pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
|
pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
|
end
|
end
|
else
|
else
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
upd_done <= 1'b1;
|
upd_done <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else if (probe) begin
|
else if (probe) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
pte_key <= pt_key;
|
pte_key <= pt_key;
|
pte_last <= pt_last;
|
pte_last <= pt_last;
|
pte_drwx <= pt_drwx;
|
pte_drwx <= pt_drwx;
|
probe_done <= 1'b1;
|
probe_done <= 1'b1;
|
end
|
end
|
else
|
else
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
goto(S_IDLE);
|
goto(S_IDLE);
|
end
|
end
|
else if (~ack_i) begin
|
else if (~ack_i) begin
|
if (keymatch) begin
|
if (keymatch) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
we_o <= we_i & pt_drwx[1];
|
we_o <= we_i & pt_drwx[1];
|
if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
|
if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
|
if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
|
if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
|
if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
|
if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
|
padr_o <= {pt_ad,vadr_i[12:0]};
|
padr_o <= {pt_ad,vadr_i[12:0]};
|
end
|
end
|
else begin
|
else begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
padr_o <= 32'hFFFFFFF8;
|
padr_o <= 32'hFFFFFFF8;
|
prv_o <= 1'b1;
|
prv_o <= 1'b1;
|
end
|
end
|
goto(S_ACK);
|
goto(S_ACK);
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
pt_ad <= {pt_ad+8'd65};
|
pt_ad <= {pt_ad+8'd65};
|
goto(S_CMP4);
|
goto(S_CMP4);
|
end
|
end
|
|
|
// Wait a clock cycle for a page fault to register.
|
// Wait a clock cycle for a page fault to register.
|
S_WAIT1:
|
S_WAIT1:
|
|
if (!ack_i)
|
goto(S_IDLE);
|
goto(S_IDLE);
|
|
|
S_ACK:
|
S_ACK:
|
if (ack_i) begin
|
if (ack_i) begin
|
if (cti_i==3'b000 || cti_i==3'b111) begin
|
if (cti_i==3'b000 || cti_i==3'b111) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
goto(S_WAIT1);
|
goto(S_WAIT1);
|
end
|
end
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
|
|
task goto;
|
task goto;
|
input [3:0] nst;
|
input [3:0] nst;
|
begin
|
begin
|
state <= nst;
|
state <= nst;
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
|
|
