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https://opencores.org/ocsvn/thor/thor/trunk
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Rev 61 |
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_MPU.v
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// FT64_MPU.v
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input i24;
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input i24;
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input i25;
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input i25;
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input i26;
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input i26;
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input i27;
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input i27;
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input i28;
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input i28;
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output reg [2:0] cti_o;
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output [2:0] cti_o;
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output reg [1:0] bte_o;
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output [1:0] bte_o;
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input bok_i;
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input bok_i;
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output cyc_o;
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output cyc_o;
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output reg stb_o;
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output reg stb_o;
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input ack_i;
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input ack_i;
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input err_i;
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input err_i;
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output we_o;
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output we_o;
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output reg [7:0] sel_o;
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output [7:0] sel_o;
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output [31:0] adr_o;
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output [31:0] adr_o;
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output reg [63:0] dat_o;
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output reg [63:0] dat_o;
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input [63:0] dat_i;
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input [63:0] dat_i;
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output sr_o;
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output sr_o;
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output cr_o;
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output cr_o;
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Line 89... |
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wire [3:0] cti;
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wire [3:0] cti;
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wire [2:0] bte;
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wire [2:0] bte;
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wire cyc,stb,we;
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wire cyc,stb,we;
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wire [7:0] sel;
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wire [7:0] sel;
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(* mark_debug="true" *)
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wire [63:0] adr;
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wire [63:0] adr;
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reg [63:0] dati;
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reg [63:0] dati;
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wire [63:0] dato;
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wire [63:0] dato;
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wire [3:0] irq;
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wire [3:0] irq;
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wire [7:0] cause;
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wire [7:0] cause;
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wire exv,rdv,wrv;
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wire exv,rdv,wrv;
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wire pulse60;
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wire pulse60;
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wire sptr_o;
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wire sptr_o;
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wire [63:0] pkeys;
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wire [63:0] pkeys;
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always @(posedge clk_i)
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cti_o <= cti;
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always @(posedge clk_i)
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bte_o <= bte;
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//always @(posedge clk_i)
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//always @(posedge clk_i)
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// cyc_o <= cyc;
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// cyc_o <= cyc;
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always @(posedge clk_i)
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always @(posedge clk_i)
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stb_o <= stb;
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stb_o <= stb;
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//always @(posedge clk_i)
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//always @(posedge clk_i)
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// we_o <= we;
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// we_o <= we;
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always @(posedge clk_i)
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sel_o <= sel;
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//always @(posedge clk_i)
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//always @(posedge clk_i)
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// adr_o <= adr;
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// adr_o <= adr;
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always @(posedge clk_i)
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always @(posedge clk_i)
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dat_o <= dato;
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dat_o <= dato;
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk_i),
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.clk(clk_i),
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.pkeys_i(pkeys),
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.pkeys_i(pkeys),
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.ol_i(ol),
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.ol_i(ol),
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.bte_i(bte),
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.cti_i(cti),
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.cti_i(cti),
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.cs_i(cs_ipt),
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.cs_i(cs_ipt),
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.icl_i(icl),
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.icl_i(icl),
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.cyc_i(cyc),
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.cyc_i(cyc),
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.stb_i(stb),
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.stb_i(stb),
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.we_i(we),
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.we_i(we),
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.sel_i(sel),
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.sel_i(sel),
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.vadr_i(adr),
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.vadr_i(adr),
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.dat_i(dato),
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.dat_i(dato),
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.dat_o(ipt_dato),
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.dat_o(ipt_dato),
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.bte_o(bte_o),
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.cti_o(cti_o),
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.cyc_o(cyc_o),
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.cyc_o(cyc_o),
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.ack_i(ack),
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.ack_i(ack),
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.we_o(we_o),
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.we_o(we_o),
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.sel_o(sel_o),
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.padr_o(adr_o),
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.padr_o(adr_o),
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.exv_o(exv),
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.exv_o(exv),
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.rdv_o(rdv),
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.rdv_o(rdv),
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.wrv_o(wrv)
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.wrv_o(wrv)
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);
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);
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always @(posedge clk_i)
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always @(posedge clk_i)
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casez({pic_ack,pit_ack,crd_ack,cs_ipt})
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casez({pic_ack,pit_ack,crd_ack,cs_ipt,ack_i})
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4'b1???: dati <= {2{pic_dato}};
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5'b1????: dati <= {2{pic_dato}};
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4'b01??: dati <= {2{pit_dato}};
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5'b01???: dati <= {2{pit_dato}};
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4'b001?: dati <= crd_dato;
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5'b001??: dati <= crd_dato;
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4'b0001: dati <= ipt_dato;
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5'b0001?: dati <= ipt_dato;
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default: dati <= dat_i;
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5'b00001: dati <= dat_i;
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default: dati <= dati;
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endcase
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endcase
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always @(posedge clk_i)
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always @(posedge clk_i)
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ack <= ack_i|pic_ack|pit_ack|crd_ack|ipt_ack;
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ack <= ack_i|pic_ack|pit_ack|crd_ack|ipt_ack;
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