`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2016-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2016-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_shift.v
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// FT64_shift.v
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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//`ifndef SHL
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//`ifndef SHL
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`define IVECTOR 6'h01
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`define IVECTOR 6'h01
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`define VSHL 6'h0C
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`define VSHL 6'h0C
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`define VSHR 6'h0D
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`define VSHR 6'h0D
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`define VASR 6'h0E
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`define VASR 6'h0E
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`define RR 6'h02
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`define RR 6'h02
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`define SHIFTR 6'h2F
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`define SHIFTR 6'h2F
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`define SHIFT31 6'h0F
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`define SHIFT31 6'h0F
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`define SHIFT63 6'h1F
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`define SHIFT63 6'h1F
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`define AMO 6'h2F
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`define AMO 6'h2F
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`define AMOSHL 6'h0C
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`define AMOSHL 6'h0C
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`define AMOSHR 6'h0D
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`define AMOSHR 6'h0D
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`define AMOASR 6'h0E
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`define AMOASR 6'h0E
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`define AMOROL 6'h0F
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`define AMOROL 6'h0F
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`define AMOSHLI 6'h2C
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`define AMOSHLI 6'h2C
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`define AMOSHRI 6'h2D
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`define AMOSHRI 6'h2D
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`define AMOASRI 6'h2E
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`define AMOASRI 6'h2E
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`define AMOROLI 6'h2F
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`define AMOROLI 6'h2F
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`define SHL 3'h0
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`define SHL 3'h0
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`define SHR 3'h1
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`define SHR 3'h1
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`define ASL 3'h2
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`define ASL 3'h2
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`define ASR 3'h3
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`define ASR 3'h3
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`define ROL 3'h4
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`define ROL 3'h4
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`define ROR 3'h5
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`define ROR 3'h5
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//`endif
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//`endif
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`define HIGHWORD 127:64
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`define HIGHWORD 127:64
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module FT64_shift(instr, a, b, res, ov);
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module FT64_shift(instr, a, b, res, ov);
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parameter DMSB=63;
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parameter DMSB=63;
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parameter SUP_VECTOR = 1;
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parameter SUP_VECTOR = 1;
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input [47:0] instr;
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input [47:0] instr;
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input [DMSB:0] a;
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input [DMSB:0] a;
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input [DMSB:0] b;
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input [DMSB:0] b;
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output [DMSB:0] res;
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output [DMSB:0] res;
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reg [DMSB:0] res;
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reg [DMSB:0] res;
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output ov;
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output ov;
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parameter ROTATE_INSN = 1;
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parameter ROTATE_INSN = 1;
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wire [5:0] opcode = instr[5:0];
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wire [5:0] opcode = instr[5:0];
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wire [5:0] func = instr[31:26];
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wire [5:0] func = instr[31:26];
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wire [2:0] shiftop = instr[25:23];
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wire [2:0] shiftop = instr[25:23];
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wire [127:0] shl = {64'd0,a} << b[5:0];
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wire [127:0] shl = {64'd0,a} << b[5:0];
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wire [127:0] shr = {a,64'd0} >> b[5:0];
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wire [127:0] shr = {a,64'd0} >> b[5:0];
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assign ov = shl[127:64] != {64{a[63]}};
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assign ov = shl[127:64] != {64{a[63]}};
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always @*
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always @*
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case(opcode)
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case(opcode)
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`IVECTOR:
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`IVECTOR:
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if (SUP_VECTOR)
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if (SUP_VECTOR)
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case(func)
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case(func)
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`VSHL: res <= shl[DMSB:0];
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`VSHL: res <= shl[DMSB:0];
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`VSHR: res <= shr[`HIGHWORD];
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`VSHR: res <= shr[`HIGHWORD];
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`VASR: if (a[DMSB])
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`VASR: if (a[DMSB])
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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else
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else
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res <= shr[`HIGHWORD];
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res <= shr[`HIGHWORD];
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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else
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else
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res <= 64'd0;
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res <= 64'd0;
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`RR:
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`RR:
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case(func)
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case(func)
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`SHIFTR:
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`SHIFTR:
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case(shiftop)
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case(shiftop)
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`SHL,`ASL: res <= shl[DMSB:0];
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`SHL,`ASL: res <= shl[DMSB:0];
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`SHR: res <= shr[`HIGHWORD];
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`SHR: res <= shr[`HIGHWORD];
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`ASR: if (a[DMSB])
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`ASR: if (a[DMSB])
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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else
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else
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res <= shr[`HIGHWORD];
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res <= shr[`HIGHWORD];
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`ROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROR: res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROR: res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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`SHIFT31,
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`SHIFT31,
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`SHIFT63:
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`SHIFT63:
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case(shiftop)
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case(shiftop)
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`SHL,`ASL:res <= shl[DMSB:0];
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`SHL,`ASL:res <= shl[DMSB:0];
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`SHR: res <= shr[`HIGHWORD];
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`SHR: res <= shr[`HIGHWORD];
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`ASR: if (a[DMSB])
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`ASR: if (a[DMSB])
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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else
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else
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res <= shr[`HIGHWORD];
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res <= shr[`HIGHWORD];
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`ROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROR: res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
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`ROR: res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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`AMO:
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`AMO:
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case(func)
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case(func)
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`AMOSHL,`AMOSHLI: res <= shl[DMSB:0];
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`AMOSHL,`AMOSHLI: res <= shl[DMSB:0];
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`AMOSHR,`AMOSHRI: res <= shr[`HIGHWORD];
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`AMOSHR,`AMOSHRI: res <= shr[`HIGHWORD];
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`AMOASR,`AMOASRI: if (a[DMSB])
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`AMOASR,`AMOASRI: if (a[DMSB])
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
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else
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else
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res <= shr[`HIGHWORD];
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res <= shr[`HIGHWORD];
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`AMOROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`AMOROL: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`AMOROLI: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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`AMOROLI: res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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default: res <= 64'd0;
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default: res <= 64'd0;
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endcase
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endcase
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endmodule
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endmodule
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