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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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`include "FT64_config.vh"
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`include "FT64_config.vh"
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2011-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_TLB.v
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// FT64_TLB.v
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//
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//
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//
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//
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// TLB
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// TLB
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// The TLB contains 256 entries, that are 16 way set associative.
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// The TLB contains 256 entries, that are 16 way set associative.
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// The TLB is shared between the instruction and data streams.
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// The TLB is shared between the instruction and data streams.
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// The code is carefully constructed to not require reset signals.
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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`define TLBMissPage {DBW-13{1'b1}}
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`define TLBMissPage {DBW-13{1'b1}}
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module FT64_TLB(rst, clk, ld, done, idle, ol,
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module FT64_TLB(clk, ld, done, idle, ol,
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ASID, op, regno, dati, dato,
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ASID, op, regno, dati, dato,
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uncached,
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uncached,
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icl_i, cyc_i, we_i, vadr_i, cyc_o, we_o, padr_o,
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icl_i, cyc_i, we_i, vadr_i, cyc_o, we_o, padr_o,
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wrv_o, rdv_o, exv_o,
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wrv_o, rdv_o, exv_o,
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TLBMiss, HTLBVirtPageo);
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TLBMiss, HTLBVirtPageo);
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parameter INC1 = 4'd2;
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parameter INC1 = 4'd2;
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parameter INC2 = 4'd3;
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parameter INC2 = 4'd3;
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parameter INC3 = 4'd4;
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parameter INC3 = 4'd4;
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parameter AGE1 = 4'd5;
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parameter AGE1 = 4'd5;
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parameter AGE2 = 4'd6;
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parameter AGE2 = 4'd6;
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input rst;
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input clk;
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input clk;
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input ld;
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input ld;
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output done;
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output done;
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output idle;
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output idle;
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input [1:0] ol; // operating level
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input [1:0] ol; // operating level
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input [ABW-1:0] vadr_i;
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input [ABW-1:0] vadr_i;
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output reg [ABW-1:0] padr_o;
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output reg [ABW-1:0] padr_o = 64'hFFFFFFFFFFFC0100;
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output uncached;
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output uncached;
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input icl_i;
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input icl_i;
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input cyc_i;
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input cyc_i;
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input we_i;
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input we_i;
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Line 76... |
output TLBMiss;
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output TLBMiss;
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output [DBW-1:0] HTLBVirtPageo;
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output [DBW-1:0] HTLBVirtPageo;
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integer n;
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integer n;
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reg [3:0] state;
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reg [1:0] state = IDLE;
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assign done = state==(IDLE && !ld) || state==TWO;
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assign done = state==(IDLE && !ld) || state==TWO;
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assign idle = state==IDLE && !ld;
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assign idle = state==IDLE && !ld;
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// Holding registers
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// Holding registers
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// These allow the TLB to updated in a single cycle as a unit
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// These allow the TLB to updated in a single cycle as a unit
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reg [7:0] HTLBPL;
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reg [7:0] HTLBPL;
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reg [2:0] HTLBPageSize;
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reg [2:0] HTLBPageSize;
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reg HTLBValid;
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reg HTLBValid;
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reg [ABW-1:0] miss_addr;
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reg [ABW-1:0] miss_addr;
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reg TLBenabled;
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reg TLBenabled = 1'b0;
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reg [7:0] i;
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reg [7:0] i = 8'h00;
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reg [DBW-1:0] Index;
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reg [DBW-1:0] Index;
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reg [3:0] Random;
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reg [3:0] Random = 4'hF;
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reg [3:0] Wired;
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reg [3:0] Wired = 4'd0;
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reg [2:0] PageSize;
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reg [2:0] PageSize;
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reg [15:0] Match;
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reg [15:0] Match;
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reg [4:0] q;
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reg [4:0] q;
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wire doddpage;
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wire doddpage;
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reg [7:0] TLBPL [ENTRIES-1:0];
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reg [7:0] TLBPL [ENTRIES-1:0];
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reg [2:0] TLBPageSize [255:0];
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reg [2:0] TLBPageSize [255:0];
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reg [ENTRIES-1:0] TLBValid;
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reg [ENTRIES-1:0] TLBValid;
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reg [DBW-1:0] imiss_addr;
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reg [DBW-1:0] imiss_addr;
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reg [DBW-1:0] dmiss_addr;
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reg [DBW-1:0] dmiss_addr;
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reg [DBW-1:0] PageTblAddr;
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reg [DBW-1:0] PageTblAddr = {DBW{1'b0}};
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reg [DBW-1:0] PageTblCtrl;
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reg [DBW-1:0] PageTblCtrl = {DBW{1'b0}};
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reg [23:0] age_lmt;
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reg [23:0] age_lmt = 24'd20000;
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reg [23:0] age_ctr;
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reg [23:0] age_ctr = 24'd0;
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wire age_tick = age_ctr < 24'd5;
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wire age_tick = age_ctr < 24'd5;
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reg cyc_en, age_en;
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reg cyc_en = 1'b1, age_en = 1'b1;
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reg [3:0] ar_state;
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reg [3:0] ar_state = IDLE;
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reg ar_wr;
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reg ar_wr = 1'b0;
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reg [7:0] age_adr, ar_adr;
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reg [7:0] age_adr = 8'h00, ar_adr = 8'h00;
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reg [32:0] count;
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reg [32:0] count;
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reg [31:0] ar_dati;
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reg [31:0] ar_dati;
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wire [31:0] ar_dato;
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wire [31:0] ar_dato;
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reg [31:0] ar_cdato;
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reg [31:0] ar_cdato;
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reg getset_age;
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reg getset_age;
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reg doLoad;
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reg doLoad = 1'b0;
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/*
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/*
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initial begin
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initial begin
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for (n = 0; n < ENTRIES; n = n + 1)
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for (n = 0; n < ENTRIES; n = n + 1)
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begin
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begin
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.o0(tlbXo0),
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.o0(tlbXo0),
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.o1(tlbXo1)
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.o1(tlbXo1)
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);
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);
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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begin
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age_ctr <= 24'd0;
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// age_ctr > age_lmt when counter hits -1, saves comparing to zero as well
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end
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if (age_ctr > age_lmt)
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else begin
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if (age_ctr==24'd0)
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age_ctr <= age_lmt;
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age_ctr <= age_lmt;
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else
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else
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age_ctr <= age_ctr - 4'd1;
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age_ctr <= age_ctr - 4'd1;
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end
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end
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// Handle Random register
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// Handle Random register
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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begin
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Random <= 4'hF;
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end
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else begin
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if (Random==Wired)
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if (Random==Wired)
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Random <= 4'hF;
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Random <= 4'hF;
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else
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else
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Random <= Random - 4'd1;
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Random <= Random - 4'd1;
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// Why would we want to update since random changes on the next clock
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// Why would we want to update since random changes on the next clock
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Random <= dati[3:0];
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Random <= dati[3:0];
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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begin
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state <= IDLE;
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end
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else begin
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case(state)
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case(state)
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IDLE:
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IDLE:
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if (ld)
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if (ld)
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state <= ONE;
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state <= ONE;
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ONE:
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ONE:
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Line 268... |
endcase
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endcase
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end
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end
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// Set index to page table
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// Set index to page table
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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i <= 8'd0;
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end
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else begin
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if (state==ONE) begin
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if (state==ONE) begin
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case(op)
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case(op)
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`TLB_RD,`TLB_WI:
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`TLB_RD,`TLB_WI:
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i <= {Index[7:4],(HTLBVirtPage >> {HTLBPageSize,1'b0}) & 4'hF};
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i <= {Index[7:4],(HTLBVirtPage >> {HTLBPageSize,1'b0}) & 4'hF};
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`TLB_WR:
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`TLB_WR:
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i <= {Random,(HTLBVirtPage >> {HTLBPageSize,1'b0}) & 4'hF};
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i <= {Random,(HTLBVirtPage >> {HTLBPageSize,1'b0}) & 4'hF};
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endcase
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endcase
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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begin
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TLBenabled <= 1'b0;
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Wired <= 4'd0;
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PageTblAddr <= {DBW{1'b0}};
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PageTblCtrl <= {DBW{1'b0}};
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age_lmt <= 24'd20000;
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end
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else begin
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if (miss_addr == {DBW{1'b0}} && TLBMiss)
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if (miss_addr == {DBW{1'b0}} && TLBMiss)
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miss_addr <= vadr_i;
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miss_addr <= vadr_i;
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if (state==ONE) begin
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if (state==ONE) begin
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case(op)
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case(op)
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Line 405... |
endcase
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endcase
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TLBAgeRam uar1(clk,ar_wr,ar_adr,ar_dati,ar_dato);
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TLBAgeRam uar1(clk,ar_wr,ar_adr,ar_dati,ar_dato);
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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begin
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age_adr <= 4'd0;
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ar_wr <= 1'b0;
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ar_adr <= 4'd0;
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ar_state <= IDLE;
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cyc_en <= 1'b1;
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age_en <= 1'b1;
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doLoad <= 1'b0;
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end
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else begin
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ar_wr <= 1'b0;
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ar_wr <= 1'b0;
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getset_age <= 1'b0;
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getset_age <= 1'b0;
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if (ld)
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if (ld)
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doLoad <= 1'b1;
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doLoad <= 1'b1;
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case(ar_state)
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case(ar_state)
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Line 487... |
if (Match[n]) q = n;
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if (Match[n]) q = n;
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end
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end
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assign uncached = TLBC[{q[3:0],vadrs[3:0]}]==3'd1;// || unmappedDataArea;
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assign uncached = TLBC[{q[3:0],vadrs[3:0]}]==3'd1;// || unmappedDataArea;
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assign TLBMiss = TLBenabled & (!unmappedArea & (q[4] | ~TLBValid[{q[3:0],vadrs[3:0]}]) ||
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assign TLBMiss = (ol!=2'b00) && TLBenabled && (!unmappedArea & (q[4] | ~TLBValid[{q[3:0],vadrs[3:0]}]) ||
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(ol!=2'b00 && hitIOPage));
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(ol!=2'b00 && hitIOPage));
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always @(posedge clk)
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always @(posedge clk)
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cyc_o <= cyc_i & (~TLBMiss | ~TLBenabled);
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cyc_o <= cyc_i && (!TLBMiss || !TLBenabled || (ol == 2'b00));
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always @(posedge clk)
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always @(posedge clk)
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we_o <= we_i & ((~TLBMiss & tlbWo1) | ~TLBenabled);
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we_o <= we_i & ((~TLBMiss & tlbWo1) | ~TLBenabled || (ol==2'b00));
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always @(posedge clk)
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always @(posedge clk)
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wrv_o <= we_i & ~TLBMiss & ~tlbWo1 & TLBenabled;
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wrv_o <= we_i & ~TLBMiss & ~tlbWo1 & TLBenabled && (ol != 2'b00);
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always @(posedge clk)
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always @(posedge clk)
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rdv_o <= ~we_i & ~TLBMiss & ~tlbRo1 & TLBenabled;
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rdv_o <= ~we_i & ~TLBMiss & ~tlbRo1 & TLBenabled && (ol != 2'b00);
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always @(posedge clk)
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always @(posedge clk)
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exv_o <= icl_i & ~TLBMiss & ~tlbXo1 & TLBenabled;
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exv_o <= icl_i & ~TLBMiss & ~tlbXo1 & TLBenabled && (ol != 2'b00);
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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padr_o <= 32'hFFFC0100;
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else begin
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if (TLBenabled && ol != 2'b00) begin
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if (TLBenabled && ol != 2'b00) begin
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case(PageSize)
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case(PageSize)
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3'd0: padr_o[ABW-1:13] <= unmappedArea ? vadr_i[ABW-1:13] : TLBMiss ? `TLBMissPage: PFN;
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3'd0: padr_o[ABW-1:13] <= unmappedArea ? vadr_i[ABW-1:13] : TLBMiss ? `TLBMissPage: PFN;
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3'd1: padr_o[ABW-1:13] <= {unmappedArea ? vadr_i[ABW-1:15] : TLBMiss ? `TLBMissPage: PFN,vadr_i[14:13]};
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3'd1: padr_o[ABW-1:13] <= {unmappedArea ? vadr_i[ABW-1:15] : TLBMiss ? `TLBMissPage: PFN,vadr_i[14:13]};
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3'd2: padr_o[ABW-1:13] <= {unmappedArea ? vadr_i[ABW-1:17] : TLBMiss ? `TLBMissPage: PFN,vadr_i[16:13]};
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3'd2: padr_o[ABW-1:13] <= {unmappedArea ? vadr_i[ABW-1:17] : TLBMiss ? `TLBMissPage: PFN,vadr_i[16:13]};
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| Line 552... |
Line 520... |
endcase
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endcase
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padr_o[12:0] <= vadr_i[12:0];
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padr_o[12:0] <= vadr_i[12:0];
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end
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end
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else
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else
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padr_o <= vadr_i;
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padr_o <= vadr_i;
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end
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endmodule
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endmodule
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module TLBRam(clk,we,wa,i,ra0,ra1,o0,o1);
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module TLBRam(clk,we,wa,i,ra0,ra1,o0,o1);
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parameter DBW=1;
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parameter DBW=1;
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