// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_fetchbuf_x1.v
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// FT64_fetchbuf_x1.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_config.vh"
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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// FETCH
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// FETCH
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//
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//
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// fetch exactly one instructions from memory into the fetch buffer
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// fetch exactly one instructions from memory into the fetch buffer
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// unless either one of the buffers is still full, in which case we
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// unless either one of the buffers is still full, in which case we
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// do nothing (kinda like alpha approach)
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// do nothing (kinda like alpha approach)
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//
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//
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module FT64_fetchbuf_x1(rst, clk4x, clk, fcu_clk,
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module FT64_fetchbuf_x1(rst, clk4x, clk, fcu_clk,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cmpgrp,
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cmpgrp,
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freezePC, thread_en, pred_on,
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freezePC, thread_en, pred_on,
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regLR,
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regLR,
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insn0, phit,
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insn0, phit,
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threadx,
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threadx,
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branchmiss, misspc, branchmiss_thrd, predict_taken0,
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branchmiss, misspc, branchmiss_thrd, predict_taken0,
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predict_takenA, predict_takenB,
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predict_takenA, predict_takenB,
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queued1, queuedNop,
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queued1, queuedNop,
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pc0, fetchbuf, fetchbufA_v, fetchbufB_v,
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pc0, fetchbuf, fetchbufA_v, fetchbufB_v,
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fetchbufA_instr, fetchbufA_pc, fetchbufA_pbyte,
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fetchbufA_instr, fetchbufA_pc, fetchbufA_pbyte,
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fetchbufB_instr, fetchbufB_pc, fetchbufB_pbyte,
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fetchbufB_instr, fetchbufB_pc, fetchbufB_pbyte,
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fetchbuf0_instr, fetchbuf0_insln,
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fetchbuf0_instr, fetchbuf0_insln,
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fetchbuf0_thrd,
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fetchbuf0_thrd,
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fetchbuf0_pc,
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fetchbuf0_pc,
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fetchbuf0_v,
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fetchbuf0_v,
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fetchbuf0_pbyte,
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fetchbuf0_pbyte,
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codebuf0,
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codebuf0,
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btgtA, btgtB,
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btgtA, btgtB,
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nop_fetchbuf,
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nop_fetchbuf,
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take_branch0,
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take_branch0,
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stompedRets,
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stompedRets,
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panic
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panic
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);
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);
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parameter AMSB = `AMSB;
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parameter AMSB = `AMSB;
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parameter RSTPC = 64'hFFFFFFFFFFFC0100;
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parameter RSTPC = 64'hFFFFFFFFFFFC0100;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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input rst;
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input rst;
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input clk4x;
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input clk4x;
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input clk;
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input clk;
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input fcu_clk;
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input fcu_clk;
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input cs_i;
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input cs_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output ack_o;
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output ack_o;
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input we_i;
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input we_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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input [55:0] dat_i;
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input [55:0] dat_i;
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input [2:0] cmpgrp;
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input [2:0] cmpgrp;
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input freezePC;
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input freezePC;
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input thread_en;
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input thread_en;
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input pred_on;
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input pred_on;
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input [4:0] regLR;
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input [4:0] regLR;
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input [55:0] insn0;
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input [55:0] insn0;
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input phit;
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input phit;
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output threadx;
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output threadx;
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input branchmiss;
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input branchmiss;
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input [AMSB:0] misspc;
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input [AMSB:0] misspc;
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input branchmiss_thrd;
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input branchmiss_thrd;
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output predict_taken0;
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output predict_taken0;
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input predict_takenA;
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input predict_takenA;
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input predict_takenB;
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input predict_takenB;
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input queued1;
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input queued1;
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input queuedNop;
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input queuedNop;
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output reg [AMSB:0] pc0;
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output reg [AMSB:0] pc0;
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output reg fetchbuf;
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output reg fetchbuf;
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output reg fetchbufA_v;
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output reg fetchbufA_v;
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output reg fetchbufB_v;
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output reg fetchbufB_v;
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output fetchbuf0_thrd;
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output fetchbuf0_thrd;
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output reg [47:0] fetchbufA_instr;
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output reg [47:0] fetchbufA_instr;
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output reg [7:0] fetchbufA_pbyte;
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output reg [7:0] fetchbufA_pbyte;
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output reg [47:0] fetchbufB_instr;
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output reg [47:0] fetchbufB_instr;
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output reg [7:0] fetchbufB_pbyte;
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output reg [7:0] fetchbufB_pbyte;
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output reg [AMSB:0] fetchbufA_pc;
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output reg [AMSB:0] fetchbufA_pc;
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output reg [AMSB:0] fetchbufB_pc;
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output reg [AMSB:0] fetchbufB_pc;
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output [47:0] fetchbuf0_instr;
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output [47:0] fetchbuf0_instr;
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output [AMSB:0] fetchbuf0_pc;
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output [AMSB:0] fetchbuf0_pc;
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output [2:0] fetchbuf0_insln;
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output [2:0] fetchbuf0_insln;
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output fetchbuf0_v;
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output fetchbuf0_v;
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output [7:0] fetchbuf0_pbyte;
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output [7:0] fetchbuf0_pbyte;
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input [55:0] codebuf0;
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input [55:0] codebuf0;
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input [AMSB:0] btgtA;
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input [AMSB:0] btgtA;
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input [AMSB:0] btgtB;
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input [AMSB:0] btgtB;
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input [3:0] nop_fetchbuf;
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input [3:0] nop_fetchbuf;
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output take_branch0;
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output take_branch0;
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input [3:0] stompedRets;
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input [3:0] stompedRets;
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output reg [3:0] panic;
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output reg [3:0] panic;
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integer n;
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integer n;
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reg [55:0] cinsn0;
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reg [55:0] cinsn0;
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wire iclk = clk;
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//BUFH ucb1 (.I(clk), .O(iclk));
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//`include "FT64_decode.vh"
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//`include "FT64_decode.vh"
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function IsBranch;
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function IsBranch;
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input [47:0] isn;
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input [47:0] isn;
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casex(isn[`INSTRUCTION_OP])
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casex(isn[`INSTRUCTION_OP])
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`Bcc: IsBranch = TRUE;
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`Bcc: IsBranch = TRUE;
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`BLcc: IsBranch = TRUE;
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`BLcc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BNEI: IsBranch = TRUE;
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`BNEI: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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default: IsBranch = FALSE;
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default: IsBranch = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsJAL;
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function IsJAL;
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input [47:0] isn;
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input [47:0] isn;
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IsJAL = isn[`INSTRUCTION_OP]==`JAL;
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IsJAL = isn[`INSTRUCTION_OP]==`JAL;
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endfunction
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endfunction
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function IsJmp;
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function IsJmp;
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input [47:0] isn;
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input [47:0] isn;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
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endfunction
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endfunction
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function IsCall;
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function IsCall;
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input [47:0] isn;
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input [47:0] isn;
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IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
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IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
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endfunction
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endfunction
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function IsRet;
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function IsRet;
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input [47:0] isn;
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input [47:0] isn;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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endfunction
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endfunction
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function IsBrk;
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function IsBrk;
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input [47:0] isn;
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input [47:0] isn;
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IsBrk = isn[`INSTRUCTION_OP]==`BRK;
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IsBrk = isn[`INSTRUCTION_OP]==`BRK;
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endfunction
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endfunction
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function IsRTI;
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function IsRTI;
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input [47:0] isn;
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input [47:0] isn;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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endfunction
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endfunction
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function IsExec;
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function IsExec;
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input [47:0] isn;
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input [47:0] isn;
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if (isn[7:6]==2'b00)
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if (isn[7:6]==2'b00)
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`R2:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`R1:
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`R1:
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case(isn[22:18])
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case(isn[22:18])
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`EXEC: IsExec = TRUE;
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`EXEC: IsExec = TRUE;
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default: IsExec = FALSE;
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default: IsExec = FALSE;
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endcase
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endcase
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default: IsExec = FALSE;
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default: IsExec = FALSE;
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endcase
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endcase
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default: IsExec = FALSE;
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default: IsExec = FALSE;
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endcase
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endcase
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else
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else
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IsExec = FALSE;
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IsExec = FALSE;
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endfunction
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endfunction
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function [2:0] fnInsLength;
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function [2:0] fnInsLength;
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input [47:0] ins;
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input [47:0] ins;
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`ifdef SUPPORT_DCI
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`ifdef SUPPORT_DCI
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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fnInsLength = 3'd2 | pred_on;
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fnInsLength = 3'd2 | pred_on;
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else
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else
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`endif
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`endif
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case(ins[7:6])
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case(ins[7:6])
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2'd0: fnInsLength = 3'd4 | pred_on;
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2'd0: fnInsLength = 3'd4 | pred_on;
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2'd1: fnInsLength = 3'd6 | pred_on;
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2'd1: fnInsLength = 3'd6 | pred_on;
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default: fnInsLength = 3'd2 | pred_on;
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default: fnInsLength = 3'd2 | pred_on;
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endcase
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endcase
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endfunction
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endfunction
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wire [2:0] fetchbufA_inslen;
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wire [2:0] fetchbufA_inslen;
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wire [2:0] fetchbufB_inslen;
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wire [2:0] fetchbufB_inslen;
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FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen, pred_on);
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FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen, pred_on);
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FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen, pred_on);
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FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen, pred_on);
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wire [47:0] xinsn0;
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wire [47:0] xinsn0;
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FT64_iexpander ux1
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FT64_iexpander ux1
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(
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(
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.cinstr(pred_on ? insn0[23:8] : insn0[15:0]),
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.cinstr(pred_on ? insn0[23:8] : insn0[15:0]),
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.expand(xinsn0)
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.expand(xinsn0)
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);
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Table of decompressed instructions.
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// Table of decompressed instructions.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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assign ack_o = cs_i & cyc_i & stb_i;
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assign ack_o = cs_i & cyc_i & stb_i;
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`ifdef SUPPORT_DCI
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`ifdef SUPPORT_DCI
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reg [47:0] DecompressTable [0:2047];
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reg [47:0] DecompressTable [0:2047];
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always @(posedge clk)
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always @(posedge clk)
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if (cs_i & cyc_i & stb_i & we_i)
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if (cs_i & cyc_i & stb_i & we_i)
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DecompressTable[adr_i[12:3]] <= dat_i[47:0];
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DecompressTable[adr_i[12:3]] <= dat_i[47:0];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,pred_on ? insn0[23:16]:insn0[15:8]}];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,pred_on ? insn0[23:16]:insn0[15:8]}];
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`endif
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`endif
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg thread;
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reg thread;
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reg stompedRet;
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reg stompedRet;
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reg ret0Counted;
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reg ret0Counted;
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wire [AMSB:0] retpc0;
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wire [AMSB:0] retpc0;
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assign predict_taken0 = (fetchbuf==1'b0) ? ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE})
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assign predict_taken0 = (fetchbuf==1'b0) ? ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE})
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: ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE});
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: ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE});
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reg [AMSB:0] branch_pcA;
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reg [AMSB:0] branch_pcA;
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reg [AMSB:0] branch_pcB;
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reg [AMSB:0] branch_pcB;
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always @*
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always @*
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begin
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begin
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case(fetchbufA_instr[`INSTRUCTION_OP])
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case(fetchbufA_instr[`INSTRUCTION_OP])
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`RET: branch_pcA = retpc0;
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`RET: branch_pcA = retpc0;
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`JMP,`CALL:
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`JMP,`CALL:
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begin
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begin
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`ifdef JMP40
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`ifdef JMP40
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branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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`else
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`else
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branch_pcA[39:0] = {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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branch_pcA[39:0] = {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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`endif
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`endif
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branch_pcA[63:40] = fetchbufA_pc[63:40];
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branch_pcA[63:40] = fetchbufA_pc[63:40];
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end
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end
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`R2: branch_pcA = btgtA; // RTI
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`R2: branch_pcA = btgtA; // RTI
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`BRK,`JAL: branch_pcA = btgtA;
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`BRK,`JAL: branch_pcA = btgtA;
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default:
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default:
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begin
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begin
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branch_pcA[31:0] = fetchbufA_pc[31:0] +
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branch_pcA[31:0] = fetchbufA_pc[31:0] +
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((fetchbufA_instr[7:6]==2'b01) ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:23],fetchbufA_instr[17:16],1'b0} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:23],fetchbufA_instr[17:16],1'b0});
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((fetchbufA_instr[7:6]==2'b01) ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:23],fetchbufA_instr[17:16],1'b0} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:23],fetchbufA_instr[17:16],1'b0});
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branch_pcA[63:32] = fetchbufA_pc[63:32];
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branch_pcA[63:32] = fetchbufA_pc[63:32];
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end
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end
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endcase
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endcase
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end
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end
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|
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always @*
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always @*
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begin
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begin
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case(fetchbufB_instr[`INSTRUCTION_OP])
|
case(fetchbufB_instr[`INSTRUCTION_OP])
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`RET: branch_pcB = retpc0;
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`RET: branch_pcB = retpc0;
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`JMP,`CALL:
|
`JMP,`CALL:
|
begin
|
begin
|
`ifdef JMP40
|
`ifdef JMP40
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branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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`else
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`else
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branch_pcB[39:0] = {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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branch_pcB[39:0] = {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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`endif
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`endif
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branch_pcB[63:40] = fetchbufB_pc[63:40];
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branch_pcB[63:40] = fetchbufB_pc[63:40];
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end
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end
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`R2: branch_pcB = btgtB; // RTI
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`R2: branch_pcB = btgtB; // RTI
|
`BRK,`JAL: branch_pcB = btgtB;
|
`BRK,`JAL: branch_pcB = btgtB;
|
default:
|
default:
|
begin
|
begin
|
branch_pcB[31:0] = fetchbufB_pc[31:0] +
|
branch_pcB[31:0] = fetchbufB_pc[31:0] +
|
((fetchbufB_instr[7:6]==2'b01) ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:23],fetchbufB_instr[17:16],1'b0} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:23],fetchbufB_instr[17:16],1'b0});
|
((fetchbufB_instr[7:6]==2'b01) ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:23],fetchbufB_instr[17:16],1'b0} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:23],fetchbufB_instr[17:16],1'b0});
|
branch_pcB[63:32] = fetchbufB_pc[63:32];
|
branch_pcB[63:32] = fetchbufB_pc[63:32];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) || ((
|
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) || ((
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
IsRet(fetchbufA_instr)
|
IsRet(fetchbufA_instr)
|
|| IsRTI(fetchbufA_instr)|| IsBrk(fetchbufA_instr) || IsJAL(fetchbufA_instr) ||
|
|| IsRTI(fetchbufA_instr)|| IsBrk(fetchbufA_instr) || IsJAL(fetchbufA_instr) ||
|
`endif
|
`endif
|
IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)) &&
|
IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)) &&
|
fetchbufA_v);
|
fetchbufA_v);
|
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) || ((
|
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) || ((
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
IsRet(fetchbufB_instr)
|
IsRet(fetchbufB_instr)
|
|| IsRTI(fetchbufB_instr)|| IsBrk(fetchbufB_instr) || IsJAL(fetchbufB_instr) ||
|
|| IsRTI(fetchbufB_instr)|| IsBrk(fetchbufB_instr) || IsJAL(fetchbufB_instr) ||
|
`endif
|
`endif
|
IsJmp(fetchbufB_instr)||IsCall(fetchbufB_instr)) &&
|
IsJmp(fetchbufB_instr)||IsCall(fetchbufB_instr)) &&
|
fetchbufB_v);
|
fetchbufB_v);
|
|
|
wire take_branch = (fetchbuf==1'b0) ? take_branchA : take_branchB;
|
wire take_branch = (fetchbuf==1'b0) ? take_branchA : take_branchB;
|
assign take_branch0 = take_branch;
|
assign take_branch0 = take_branch;
|
|
|
/*
|
/*
|
always @*
|
always @*
|
begin
|
begin
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
end
|
end
|
*/
|
*/
|
assign threadx = fetchbuf;
|
assign threadx = fetchbuf;
|
|
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
FT64_RSB #(AMSB) ursb1
|
FT64_RSB #(AMSB) ursb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fcu_clk),
|
.clk(fcu_clk),
|
.regLR(regLR),
|
.regLR(regLR),
|
.queued1(queued1),
|
.queued1(queued1),
|
.queued2(1'b0),
|
.queued2(1'b0),
|
.fetchbuf0_v(fetchbuf0_v),
|
.fetchbuf0_v(fetchbuf0_v),
|
.fetchbuf0_pc(fetchbuf0_pc),
|
.fetchbuf0_pc(fetchbuf0_pc),
|
.fetchbuf0_instr(fetchbuf0_instr),
|
.fetchbuf0_instr(fetchbuf0_instr),
|
.fetchbuf1_v(1'b0),
|
.fetchbuf1_v(1'b0),
|
.fetchbuf1_pc(RSTPC),
|
.fetchbuf1_pc(RSTPC),
|
.fetchbuf1_instr(`NOP_INSN),
|
.fetchbuf1_instr(`NOP_INSN),
|
.stompedRets(stompedRets),
|
.stompedRets(stompedRets),
|
.stompedRet(stompedRet),
|
.stompedRet(stompedRet),
|
.pc(retpc0)
|
.pc(retpc0)
|
);
|
);
|
|
|
`else
|
`else
|
assign retpc0 = RSTPC;
|
assign retpc0 = RSTPC;
|
assign retpc1 = RSTPC;
|
assign retpc1 = RSTPC;
|
`endif
|
`endif
|
|
|
wire peclk, neclk;
|
wire peclk, neclk;
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
|
|
reg did_branch;
|
reg did_branch;
|
|
|
always @(posedge clk)
|
always @(posedge iclk)
|
if (rst) begin
|
if (rst) begin
|
pc0 <= RSTPC;
|
pc0 <= RSTPC;
|
fetchbufA_v <= 1'b0;
|
fetchbufA_v <= 1'b0;
|
fetchbufB_v <= 1'b0;
|
fetchbufB_v <= 1'b0;
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
panic <= `PANIC_NONE;
|
panic <= `PANIC_NONE;
|
did_branch <= 1'b0;
|
did_branch <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
|
|
did_branch <= take_branch & ~branchmiss;
|
did_branch <= take_branch & ~branchmiss;
|
|
|
begin
|
begin
|
|
|
// On a branch miss with threading enabled all fectch buffers are
|
// On a branch miss with threading enabled all fectch buffers are
|
// invalidated even though the data in the fetch buffer would be valid
|
// invalidated even though the data in the fetch buffer would be valid
|
// for the thread that isn't in a branchmiss state. This is done to
|
// for the thread that isn't in a branchmiss state. This is done to
|
// keep things simple. For the thread that doesn't miss the current
|
// keep things simple. For the thread that doesn't miss the current
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
// for that thread is assigned the current fetchbuf pc.
|
// for that thread is assigned the current fetchbuf pc.
|
// For the thread that misses the pc is simply assigned the misspc.
|
// For the thread that misses the pc is simply assigned the misspc.
|
if (branchmiss) begin
|
if (branchmiss) begin
|
pc0 <= misspc;
|
pc0 <= misspc;
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("Branch miss");
|
$display("Branch miss");
|
$display("misspc=%h", misspc);
|
$display("misspc=%h", misspc);
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
end
|
end
|
// else if (cinsn0[`INSTRUCTION_OP]==`CALL || cinsn0[`INSTRUCTION_OP]==`JMP) begin
|
// else if (cinsn0[`INSTRUCTION_OP]==`CALL || cinsn0[`INSTRUCTION_OP]==`JMP) begin
|
// pc0[31:0] = cinsn0[6] ? {cinsn0[47:8]} : {pc0[31:24],cinsn0[31:8]};
|
// pc0[31:0] = cinsn0[6] ? {cinsn0[47:8]} : {pc0[31:24],cinsn0[31:8]};
|
// fetchbufA_v <= `INV;
|
// fetchbufA_v <= `INV;
|
// fetchbufB_v <= `INV;
|
// fetchbufB_v <= `INV;
|
// fetchbuf <= 1'b0;
|
// fetchbuf <= 1'b0;
|
// end
|
// end
|
else if (take_branch) begin
|
else if (take_branch) begin
|
if (fetchbuf == 1'b0) begin
|
if (fetchbuf == 1'b0) begin
|
// In this case fetchbufA must be valid, or take_branch wouldn't be.
|
// In this case fetchbufA must be valid, or take_branch wouldn't be.
|
case(fetchbufB_v)
|
case(fetchbufB_v)
|
1'b0:
|
1'b0:
|
begin
|
begin
|
pc0 <= branch_pcA;
|
pc0 <= branch_pcA;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= (queued1|queuedNop);
|
fetchbuf <= (queued1|queuedNop);
|
end
|
end
|
1'b1:
|
1'b1:
|
if (did_branch) begin
|
if (did_branch) begin
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= (queued1|queuedNop);
|
fetchbuf <= (queued1|queuedNop);
|
FetchB();
|
FetchB();
|
end
|
end
|
else
|
else
|
begin
|
begin
|
pc0 <= branch_pcA;
|
pc0 <= branch_pcA;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbuf <= (queued1|queuedNop);
|
fetchbuf <= (queued1|queuedNop);
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
else begin
|
else begin
|
case(fetchbufA_v)
|
case(fetchbufA_v)
|
1'b0:
|
1'b0:
|
begin
|
begin
|
pc0 <= branch_pcB;
|
pc0 <= branch_pcB;
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbuf <= !(queued1|queuedNop);
|
fetchbuf <= !(queued1|queuedNop);
|
end
|
end
|
1'b1:
|
1'b1:
|
if (did_branch) begin
|
if (did_branch) begin
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbuf <= ~(queued1|queuedNop);
|
fetchbuf <= ~(queued1|queuedNop);
|
FetchA();
|
FetchA();
|
end
|
end
|
else
|
else
|
begin
|
begin
|
pc0 <= branch_pcB;
|
pc0 <= branch_pcB;
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
fetchbuf <= !(queued1|queuedNop);
|
fetchbuf <= !(queued1|queuedNop);
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end // if branch
|
end // if branch
|
|
|
else begin // there is no branchback in the system
|
else begin // there is no branchback in the system
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
// there are no backwards branches in the mix
|
// there are no backwards branches in the mix
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, (queued1|queuedNop)})
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, (queued1|queuedNop)})
|
2'b00: ; // do nothing
|
2'b00: ; // do nothing
|
2'b10: ;
|
2'b10: ;
|
2'b11: begin fetchbufA_v <= `INV; fetchbuf <= ~fetchbuf; end
|
2'b11: begin fetchbufA_v <= `INV; fetchbuf <= ~fetchbuf; end
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
endcase
|
endcase
|
else case ({fetchbufB_v, (queued1|queuedNop)})
|
else case ({fetchbufB_v, (queued1|queuedNop)})
|
2'b00: ; // do nothing
|
2'b00: ; // do nothing
|
2'b10: ;
|
2'b10: ;
|
2'b11: begin fetchbufB_v <= `INV; fetchbuf <= ~fetchbuf; end
|
2'b11: begin fetchbufB_v <= `INV; fetchbuf <= ~fetchbuf; end
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
endcase
|
endcase
|
//
|
//
|
// get data iff the fetch buffers are empty
|
// get data iff the fetch buffers are empty
|
//
|
//
|
if (fetchbufA_v == `INV) begin
|
if (fetchbufA_v == `INV) begin
|
FetchA();
|
FetchA();
|
// fetchbuf steering logic correction
|
// fetchbuf steering logic correction
|
if (fetchbufB_v==`INV && phit)
|
if (fetchbufB_v==`INV && phit)
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
end
|
end
|
else if (fetchbufB_v == `INV) begin
|
else if (fetchbufB_v == `INV) begin
|
FetchB();
|
FetchB();
|
end
|
end
|
end
|
end
|
//
|
//
|
// get data iff the fetch buffers are empty
|
// get data iff the fetch buffers are empty
|
//
|
//
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
FetchA();
|
FetchA();
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
end
|
end
|
// // Steer fetchbuf to the valid buffer.
|
// // Steer fetchbuf to the valid buffer.
|
// else if (fetchbufB_v == `INV)
|
// else if (fetchbufB_v == `INV)
|
// fetchbuf <= 1'b0;
|
// fetchbuf <= 1'b0;
|
// else if (fetchbufA_v == `INV)
|
// else if (fetchbufA_v == `INV)
|
// fetchbuf <= 1'b1;
|
// fetchbuf <= 1'b1;
|
// else if (fetchbufA_v == `INV) begin
|
// else if (fetchbufA_v == `INV) begin
|
// FetchA();
|
// FetchA();
|
// end
|
// end
|
// else if (fetchbufB_v == `INV) begin
|
// else if (fetchbufB_v == `INV) begin
|
// FetchB();
|
// FetchB();
|
// end
|
// end
|
end
|
end
|
|
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
// queue.
|
// queue.
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
end
|
end
|
|
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufB_instr;
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufB_instr;
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufB_inslen;
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufB_inslen;
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufB_v ;
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufB_v ;
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufB_pc ;
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufB_pc ;
|
assign fetchbuf0_thrd = 1'b0;
|
assign fetchbuf0_thrd = 1'b0;
|
assign fetchbuf0_pbyte = (fetchbuf == 1'b0) ? fetchbufA_pbyte : fetchbufB_pbyte;
|
assign fetchbuf0_pbyte = (fetchbuf == 1'b0) ? fetchbufA_pbyte : fetchbufB_pbyte;
|
|
|
reg [2:0] insln0;
|
reg [2:0] insln0;
|
always @*
|
always @*
|
begin
|
begin
|
`ifdef SUPPORT_DCI
|
`ifdef SUPPORT_DCI
|
if (insn0[5:0]==`CMPRSSD)
|
if (insn0[5:0]==`CMPRSSD)
|
insln0 <= 3'd2 | pred_on;
|
insln0 <= 3'd2 | pred_on;
|
else
|
else
|
`endif
|
`endif
|
if (IsExec(insn0))
|
if (IsExec(insn0))
|
insln0 <= fnInsLength(codebuf0); //???? should be 4?
|
insln0 <= fnInsLength(codebuf0); //???? should be 4?
|
else
|
else
|
insln0 <= fnInsLength(insn0);
|
insln0 <= fnInsLength(insn0);
|
end
|
end
|
|
|
|
|
always @*
|
always @*
|
begin
|
begin
|
`ifdef SUPPORT_DCI
|
`ifdef SUPPORT_DCI
|
if (insn0[13:8]==`CMPRSSD && pred_on)
|
if (insn0[13:8]==`CMPRSSD && pred_on)
|
cinsn0 <= expand0;
|
cinsn0 <= expand0;
|
else if (insn0[5:0]==`CMPRSSD && !pred_on)
|
else if (insn0[5:0]==`CMPRSSD && !pred_on)
|
cinsn0 <= expand0;
|
cinsn0 <= expand0;
|
else
|
else
|
`endif
|
`endif
|
if (IsExec(insn0) && !pred_on)
|
if (IsExec(insn0) && !pred_on)
|
cinsn0 <= codebuf0;
|
cinsn0 <= codebuf0;
|
else if (IsExec(insn0[55:8]) && pred_on)
|
else if (IsExec(insn0[55:8]) && pred_on)
|
cinsn0 <= codebuf0;
|
cinsn0 <= codebuf0;
|
else if (insn0[15] & pred_on)
|
else if (insn0[15] & pred_on)
|
cinsn0 <= {xinsn0,insn0[7:0]};
|
cinsn0 <= {xinsn0,insn0[7:0]};
|
else if (insn0[7] & ~pred_on)
|
else if (insn0[7] & ~pred_on)
|
cinsn0 <= xinsn0;
|
cinsn0 <= xinsn0;
|
else
|
else
|
cinsn0 <= insn0;
|
cinsn0 <= insn0;
|
end
|
end
|
|
|
task FetchA;
|
task FetchA;
|
begin
|
begin
|
fetchbufA_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
fetchbufA_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
fetchbufA_pbyte = cinsn0[7:0];
|
fetchbufA_pbyte = cinsn0[7:0];
|
fetchbufA_v <= `VAL;
|
fetchbufA_v <= `VAL;
|
fetchbufA_pc <= pc0;
|
fetchbufA_pc <= pc0;
|
if (phit && ~freezePC)
|
if (phit && ~freezePC)
|
pc0 <= pc0 + insln0;
|
pc0[31:0] <= pc0[31:0] + insln0;
|
else
|
// else
|
pc0 <= pc0;
|
// pc0 <= pc0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task FetchB;
|
task FetchB;
|
begin
|
begin
|
fetchbufB_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
fetchbufB_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
fetchbufB_pbyte = cinsn0[7:0];
|
fetchbufB_pbyte = cinsn0[7:0];
|
fetchbufB_v <= `VAL;
|
fetchbufB_v <= `VAL;
|
fetchbufB_pc <= pc0;
|
fetchbufB_pc <= pc0;
|
if (phit && ~freezePC)
|
if (phit && ~freezePC)
|
pc0 <= pc0 + insln0;
|
pc0[31:0] <= pc0[31:0] + insln0;
|
else
|
// else
|
pc0 <= pc0;
|
// pc0 <= pc0;
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
