| Line 24... |
Line 24... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "Thor_defines.v"
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`include "Thor_defines.v"
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module Thor_alu(corenum, rst, clk, alu_ld, alu_op, alu_fn, alu_argA, alu_argB, alu_argC, alu_argI, alu_pc, insnsz, o, alu_done, alu_divByZero);
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module Thor_alu(corenum, rst, clk, alu_ld, alu_abort, alu_op, alu_fn, alu_argA, alu_argB, alu_argC, alu_argI, alu_pc, insnsz, o, alu_done, alu_idle, alu_divByZero);
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parameter DBW=64;
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parameter DBW=64;
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parameter BIG=1;
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parameter BIG=1;
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parameter FEATURES = 0;
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parameter FEATURES = 0;
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input [63:0] corenum;
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input [63:0] corenum;
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input rst;
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input rst;
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input clk;
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input clk;
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input alu_ld;
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input alu_ld;
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input alu_abort;
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input [7:0] alu_op;
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input [7:0] alu_op;
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input [5:0] alu_fn;
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input [5:0] alu_fn;
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input [DBW-1:0] alu_argA;
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input [DBW-1:0] alu_argA;
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input [DBW-1:0] alu_argB;
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input [DBW-1:0] alu_argB;
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input [DBW-1:0] alu_argC;
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input [DBW-1:0] alu_argC;
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input [DBW-1:0] alu_argI;
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input [DBW-1:0] alu_argI;
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input [DBW-1:0] alu_pc;
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input [DBW-1:0] alu_pc;
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input [3:0] insnsz;
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input [3:0] insnsz;
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output reg [DBW-1:0] o;
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output reg [DBW-1:0] o;
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output reg alu_done;
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output reg alu_done;
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output reg alu_idle;
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output alu_divByZero;
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output alu_divByZero;
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wire signed [DBW-1:0] alu_argAs = alu_argA;
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wire signed [DBW-1:0] alu_argAs = alu_argA;
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wire signed [DBW-1:0] alu_argBs = alu_argB;
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wire signed [DBW-1:0] alu_argBs = alu_argB;
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wire signed [DBW-1:0] alu_argIs = alu_argI;
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wire signed [DBW-1:0] alu_argIs = alu_argI;
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| Line 56... |
Line 58... |
wire [7:0] bcdao,bcdso;
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wire [7:0] bcdao,bcdso;
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wire [15:0] bcdmo;
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wire [15:0] bcdmo;
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wire [DBW-1:0] bf_out;
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wire [DBW-1:0] bf_out;
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wire [DBW-1:0] shfto;
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wire [DBW-1:0] shfto;
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wire alu_mult_done,alu_div_done;
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wire alu_mult_done,alu_div_done;
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wire alu_mult_idle,alu_div_idle;
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wire [DBW-1:0] p_out;
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wire [DBW-1:0] p_out;
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reg [3:0] o1;
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reg [3:0] o1;
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integer n;
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integer n;
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Thor_multiplier #(DBW) umult1
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Thor_multiplier #(DBW) umult1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`MUL || alu_fn==`MULU)) || alu_op==`MULI || alu_op==`MULUI)),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`MUL || alu_fn==`MULU)) || alu_op==`MULI || alu_op==`MULUI)),
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.abort(alu_abort),
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.sgn((alu_op==`RR && alu_op==`MUL) || alu_op==`MULI),
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.sgn((alu_op==`RR && alu_op==`MUL) || alu_op==`MULI),
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.isMuli(alu_op==`MULI || alu_op==`MULUI),
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.isMuli(alu_op==`MULI || alu_op==`MULUI),
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.a(alu_argA),
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.a(alu_argA),
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.b(alu_argB),
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.b(alu_argB),
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.imm(alu_argI),
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.imm(alu_argI),
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.o(alu_prod),
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.o(alu_prod),
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.done(alu_mult_done)
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.done(alu_mult_done),
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.idle(alu_mult_idle)
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);
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);
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Thor_divider #(DBW) udiv1
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Thor_divider #(DBW) udiv1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`DIV || alu_fn==`DIVU)) || alu_op==`DIVI || alu_op==`DIVUI)),
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.ld(alu_ld && ((alu_op==`RR && (alu_fn==`DIV || alu_fn==`DIVU || alu_fn==`MOD || alu_fn==`MODU))
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.sgn((alu_op==`RR && alu_fn==`DIV) || alu_op==`DIVI),
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|| alu_op==`DIVI || alu_op==`DIVUI || alu_op==`MODI || alu_op==`MODUI)),
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.isDivi(alu_op==`DIVI || alu_op==`DIVUI),
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.abort(alu_abort),
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.sgn((alu_op==`RR && (alu_fn==`DIV || alu_fn==`MOD)) || alu_op==`DIVI || alu_op==`MODI),
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.isDivi(alu_op==`DIVI || alu_op==`DIVUI || alu_op==`MODI || alu_op==`MODUI),
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.a(alu_argA),
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.a(alu_argA),
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.b(alu_argB),
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.b(alu_argB),
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.imm(alu_argI),
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.imm(alu_argI),
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.qo(alu_divq),
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.qo(alu_divq),
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.ro(alu_rem),
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.ro(alu_rem),
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.dvByZr(alu_divByZero),
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.dvByZr(alu_divByZero),
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.done(alu_div_done)
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.done(alu_div_done),
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.idle(alu_div_idle)
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);
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);
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Thor_shifter #(DBW) ushft0
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Thor_shifter #(DBW) ushft0
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(
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(
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.func(alu_fn),
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.func(alu_fn),
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| Line 197... |
Line 205... |
`_16ADDU: o <= {alu_argA[DBW-5:0],4'b0} + alu_argB;
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`_16ADDU: o <= {alu_argA[DBW-5:0],4'b0} + alu_argB;
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`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
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`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
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`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
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`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
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`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`MOD,`MODU: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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endcase
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`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`MODI,`MODUI: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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`_2ADDUI: o <= {alu_argA[DBW-2:0],1'b0} + alu_argI;
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`_2ADDUI: o <= {alu_argA[DBW-2:0],1'b0} + alu_argI;
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`_4ADDUI: o <= {alu_argA[DBW-3:0],2'b0} + alu_argI;
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`_4ADDUI: o <= {alu_argA[DBW-3:0],2'b0} + alu_argI;
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`_8ADDUI: o <= {alu_argA[DBW-4:0],3'b0} + alu_argI;
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`_8ADDUI: o <= {alu_argA[DBW-4:0],3'b0} + alu_argI;
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`_16ADDUI: o <= {alu_argA[DBW-5:0],4'b0} + alu_argI;
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`_16ADDUI: o <= {alu_argA[DBW-5:0],4'b0} + alu_argI;
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`R:
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`R:
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| Line 345... |
Line 355... |
8'h10,8'h11,8'h12,8'h13,8'h14,8'h15,8'h16,8'h17,8'h18,8'h19,8'h1A,8'h1B,8'h1C,8'h1D,8'h1E,8'h1f:
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8'h10,8'h11,8'h12,8'h13,8'h14,8'h15,8'h16,8'h17,8'h18,8'h19,8'h1A,8'h1B,8'h1C,8'h1D,8'h1E,8'h1f:
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begin
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begin
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case(alu_fn)
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case(alu_fn)
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2'd0: begin // ICMP
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2'd0: begin // ICMP
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o1[0] = alu_argA == alu_argB;
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o1[0] = alu_argA == alu_argB;
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o1[1] = alu_argAs < alu_argBs;
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o1[1] = ($signed(alu_argA) < $signed(alu_argB));
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o1[2] = alu_argA < alu_argB;
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o1[2] = alu_argA < alu_argB;
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o1[3] = 1'b0;
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o1[3] = 1'b0;
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o <= {16{o1}};
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o <= {16{o1}};
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end
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end
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`ifdef FLOATING_POINT
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`ifdef FLOATING_POINT
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| Line 373... |
Line 383... |
end
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end
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// CMPI
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// CMPI
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8'h20,8'h21,8'h22,8'h23,8'h24,8'h25,8'h26,8'h27,8'h28,8'h29,8'h2A,8'h2B,8'h2C,8'h2D,8'h2E,8'h2f:
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8'h20,8'h21,8'h22,8'h23,8'h24,8'h25,8'h26,8'h27,8'h28,8'h29,8'h2A,8'h2B,8'h2C,8'h2D,8'h2E,8'h2f:
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begin
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begin
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o1[0] = alu_argA == alu_argI;
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o1[0] = alu_argA == alu_argI;
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o1[1] = alu_argAs < alu_argIs;
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o1[1] = ($signed(alu_argA) < $signed(alu_argI));
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o1[2] = alu_argA < alu_argI;
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o1[2] = alu_argA < alu_argI;
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o1[3] = 1'b0;
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o1[3] = 1'b0;
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o <= {16{o1}};
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o <= {16{o1}};
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end
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end
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`LLA,
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`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`SB,`SC,`SH,`SW,`CAS,`LVB,`LVC,`LVH,`LVW,`STI,
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`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`SB,`SC,`SH,`SW,`CAS,`LVB,`LVC,`LVH,`LVW,`STI,
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`LWS,`SWS,`RTS2,`STS,`STFND,`STCMP,`PUSH:
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`LWS,`SWS,`STS,`STFND,`STCMP,`PUSH:
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begin
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begin
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o <= alu_argA + alu_argC + alu_argI;
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o <= alu_argA + alu_argC + alu_argI;
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end
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end
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`JMPI: o <= {alu_argA << alu_fn[1:0]} + alu_argC + alu_argI;
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`JMPI: o <= {alu_argA << alu_fn[1:0]} + alu_argC + alu_argI;
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`LBX,`LBUX,`SBX,
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`LBX,`LBUX,`SBX,
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`LCX,`LCUX,`SCX,
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`LCX,`LCUX,`SCX,
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`LHX,`LHUX,`SHX,
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`LHX,`LHUX,`SHX,
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`LWX,`SWX,
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`LWX,`SWX,`LLAX,
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`JMPIX:
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`JMPIX:
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case(alu_fn[1:0])
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case(alu_fn[1:0])
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2'd0: o <= alu_argA + alu_argC + alu_argB;
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2'd0: o <= alu_argA + alu_argC + alu_argB;
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2'd1: o <= alu_argA + alu_argC + {alu_argB,1'b0};
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2'd1: o <= alu_argA + alu_argC + {alu_argB,1'b0};
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2'd2: o <= alu_argA + alu_argC + {alu_argB,2'b0};
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2'd2: o <= alu_argA + alu_argC + {alu_argB,2'b0};
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| Line 434... |
Line 445... |
always @*
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always @*
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case(alu_op)
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case(alu_op)
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`RR:
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`RR:
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case(alu_fn)
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case(alu_fn)
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`MUL,`MULU: alu_done <= alu_mult_done;
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`MUL,`MULU: alu_done <= alu_mult_done;
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`DIV,`DIVU: alu_done <= alu_div_done;
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`DIV,`DIVU,`MOD,`MODU: alu_done <= alu_div_done;
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default: alu_done <= `TRUE;
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default: alu_done <= `TRUE;
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endcase
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endcase
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`MULI,`MULUI: alu_done <= alu_mult_done;
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`MULI,`MULUI: alu_done <= alu_mult_done;
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`DIVI,`DIVUI: alu_done <= alu_div_done;
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`DIVI,`DIVUI,`MODI,`MODUI: alu_done <= alu_div_done;
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default: alu_done <= `TRUE;
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default: alu_done <= `TRUE;
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endcase
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endcase
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// Generate idle signal
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always @*
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case(alu_op)
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`RR:
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case(alu_fn)
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`MUL,`MULU: alu_idle <= alu_mult_idle;
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`DIV,`DIVU,`MOD,`MODU: alu_idle <= alu_div_idle;
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default: alu_idle <= `TRUE;
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endcase
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`MULI,`MULUI: alu_idle <= alu_mult_idle;
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`DIVI,`DIVUI,`MODI,`MODUI: alu_idle <= alu_div_idle;
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default: alu_idle <= `TRUE;
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endcase
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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