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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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wire faz = alu_argA[DBW-2:0]==63'd0;
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wire faz = alu_argA[DBW-2:0]==63'd0;
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wire fbz = alu_argB[DBW-2:0]==63'd0;
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wire fbz = alu_argB[DBW-2:0]==63'd0;
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wire feq = (faz & fbz) || (alu_argA==alu_argB); // special test for zero
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wire feq = (faz & fbz) || (alu_argA==alu_argB); // special test for zero
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wire fgt1 = alu_argA[DBW-2:0] > alu_argB[DBW-2:0];
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wire fgt1 = alu_argA[DBW-2:0] > alu_argB[DBW-2:0];
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wire flt1 = alu_argA[DBW-2:0] < alu_argB[DBW-2:0];
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wire flt1 = alu_argA[DBW-2:0] < alu_argB[DBW-2:0];
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wire flt = alu_argA[DBW] ^ alu_argB[DBW] ? alu_argA[DBW] & !(faz & fbz): alu_argA[DBW] ? fgt1 : flt1;
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wire flt = alu_argA[DBW-1] ^ alu_argB[DBW-1] ? alu_argA[DBW-1] & !(faz & fbz): alu_argA[DBW-1] ? fgt1 : flt1;
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wire nanA = DBW==32 ? alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0) : alu_argA[62:52]==11'h7FF && (alu_argA[51:0]!=52'd0);
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wire nanA = DBW==32 ? alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0) : alu_argA[62:52]==11'h7FF && (alu_argA[51:0]!=52'd0);
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wire nanB = DBW==32 ? alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0) : alu_argB[62:52]==11'h7FF && (alu_argB[51:0]!=52'd0);
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wire nanB = DBW==32 ? alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0) : alu_argB[62:52]==11'h7FF && (alu_argB[51:0]!=52'd0);
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wire fsaz = alu_argA[30:0]==31'd0;
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wire fsaz = alu_argA[30:0]==31'd0;
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wire fsbz = alu_argB[30:0]==31'd0;
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wire fsbz = alu_argB[30:0]==31'd0;
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`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
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`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
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`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
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`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
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`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`MOD,`MODU: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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`MOD,`MODU: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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`CHK: o <= ($signed(alu_argC) >= $signed(alu_argA)) && ($signed(alu_argC) < $signed(alu_argB));
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default: o <= 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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endcase
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`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
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`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
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`MODI,`MODUI: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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`MODI,`MODUI: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
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`R:
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`R:
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case(alu_fn[3:0])
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case(alu_fn[3:0])
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`MOV: o <= alu_argA;
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`MOV: o <= alu_argA;
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`NEG: o <= -alu_argA;
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`NEG: o <= -alu_argA;
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`NOT: o <= |alu_argA ? 64'd0 : 64'd1;
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`NOT: o <= |alu_argA ? 64'd0 : 64'd1;
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`ABS: o <= BIG ? (alu_argA[DBW] ? -alu_argA : alu_argA) : 64'hDEADDEADDEADDEAD;
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`ABS: o <= BIG ? (alu_argA[DBW-1] ? -alu_argA : alu_argA) : 64'hDEADDEADDEADDEAD;
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`SGN: o <= BIG ? (alu_argA[DBW] ? 64'hFFFFFFFFFFFFFFFF : alu_argA==64'd0 ? 64'd0 : 64'd1) : 64'hDEADDEADDEADDEAD;
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`SGN: o <= BIG ? (alu_argA[DBW-1] ? 64'hFFFFFFFFFFFFFFFF : alu_argA==64'd0 ? 64'd0 : 64'd1) : 64'hDEADDEADDEADDEAD;
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`CNTLZ: o <= BIG ? cntlzo : 64'hDEADDEADDEADDEAD;
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`CNTLZ: o <= BIG ? cntlzo : 64'hDEADDEADDEADDEAD;
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`CNTLO: o <= BIG ? cntloo : 64'hDEADDEADDEADDEAD;
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`CNTLO: o <= BIG ? cntloo : 64'hDEADDEADDEADDEAD;
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`CNTPOP: o <= BIG ? cntpopo : 64'hDEADDEADDEADDEAD;
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`CNTPOP: o <= BIG ? cntpopo : 64'hDEADDEADDEADDEAD;
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`ZXB: o <= BIG ? {56'd0,alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
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`ZXB: o <= BIG ? {56'd0,alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
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`ZXC: o <= BIG ? {48'd0,alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
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`ZXC: o <= BIG ? {48'd0,alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
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Line 287... |
end
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end
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else
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else
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o <= 64'hDEADDEADDEADDEAD;
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o <= 64'hDEADDEADDEADDEAD;
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*/
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*/
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`ADDI,`ADDUI,`ADDUIS,`LEA:
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`ADDI,`ADDUI,`ADDUIS:
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o <= alu_argA + alu_argI;
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o <= alu_argA + alu_argI;
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`SUBI,`SUBUI:
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`SUBI,`SUBUI:
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o <= alu_argA - alu_argI;
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o <= alu_argA - alu_argI;
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`ANDI: o <= alu_argA & alu_argI;
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`ANDI: o <= alu_argA & alu_argI;
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`ORI: o <= alu_argA | alu_argI;
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`ORI: o <= alu_argA | alu_argI;
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`SHIFT: o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
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`SHIFT: o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
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`ifdef BITFIELDOPS
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`ifdef BITFIELDOPS
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`BITFIELD: o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
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`BITFIELD: o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
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`endif
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`endif
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`LOOP: o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
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`LOOP: o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
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`CHKI: o <= ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
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default: o <= 64'hDEADDEADDEADDEAD;
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default: o <= 64'hDEADDEADDEADDEAD;
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endcase
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endcase
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end
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end
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// Generate done signal
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// Generate done signal
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