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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_alu.v] - Diff between revs 37 and 42

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Rev 37 Rev 42
Line 206... Line 206...
        `MIN:           o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
        `MIN:           o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
        `MAX:           o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
        `MAX:           o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
        `MUL,`MULU:     o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
        `MUL,`MULU:     o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
        `DIV,`DIVU:     o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
        `DIV,`DIVU:     o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
    `MOD,`MODU:     o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
    `MOD,`MODU:     o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
    `CHK:           o <= ($signed(alu_argC) >= $signed(alu_argA)) && ($signed(alu_argC) < $signed(alu_argB));
    `CHK,`CHKX:     o <= ($signed(alu_argC) >= $signed(alu_argA)) && ($signed(alu_argC) < $signed(alu_argB));
        default:   o <= 64'hDEADDEADDEADDEAD;
        default:   o <= 64'hDEADDEADDEADDEAD;
        endcase
        endcase
`MULI,`MULUI:   o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
`MULI,`MULUI:   o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
`DIVI,`DIVUI:   o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
`DIVI,`DIVUI:   o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
`MODI,`MODUI:   o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
`MODI,`MODUI:   o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
Line 407... Line 407...
            2'd0:   o <= alu_argA + alu_argC + alu_argB;
            2'd0:   o <= alu_argA + alu_argC + alu_argB;
            2'd1:   o <= alu_argA + alu_argC + {alu_argB,1'b0};
            2'd1:   o <= alu_argA + alu_argC + {alu_argB,1'b0};
            2'd2:   o <= alu_argA + alu_argC + {alu_argB,2'b0};
            2'd2:   o <= alu_argA + alu_argC + {alu_argB,2'b0};
            2'd3:   o <= alu_argA + alu_argC + {alu_argB,3'b0};
            2'd3:   o <= alu_argA + alu_argC + {alu_argB,3'b0};
            endcase
            endcase
 
`ifdef VECTOROPS
 
`LV,`SV:      o <= alu_argA + alu_argC + alu_argI;
 
`LVWS,`SVWS:  o <= alu_argA + alu_argC + alu_argB * alu_argI[8:3];
 
`LVX,`SVX:    o <= alu_argA + alu_argC + alu_argB;
 
`endif
`ifdef STACKOPS
`ifdef STACKOPS
`PEA,`LINK: o <= alu_argA + alu_argC - 64'd8;
`PEA,`LINK: o <= alu_argA + alu_argC - 64'd8;
`UNLINK:    o <= alu_argA + alu_argC + 64'd8;
`UNLINK:    o <= alu_argA + alu_argC + 64'd8;
`POP:       o <= alu_argA + alu_argC;
`POP:       o <= alu_argA + alu_argC;
`endif
`endif
`JSR,`JSRS,`JSRZ,`SYS:  o <= alu_pc + insnsz;
`JSR,`JSRS,`JSRZ,`SYS,`JSF:     o <= alu_pc + insnsz;
`INT:           o <= alu_pc;
`INT:           o <= alu_pc;
`MFSPR,`MTSPR:  begin
`MFSPR,`MTSPR:  begin
                o <= alu_argA;
                o <= alu_argA;
                end
                end
`MUX:   begin
`MUX:   begin
Line 436... Line 441...
`SHIFT:     o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
`SHIFT:     o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
`ifdef BITFIELDOPS
`ifdef BITFIELDOPS
`BITFIELD:      o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
`BITFIELD:      o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
`endif
`endif
`LOOP:      o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
`LOOP:      o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
`CHKI:      o <= ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
`CHKXI:   o <= ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
 
`CHKI:
 
    begin
 
        o1[0] = ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
 
        o1[1] = 1'b0;
 
        o1[2] = 1'b0;
 
        o1[3] = 1'b0;
 
        o <= {16{o1}};
 
    end
default:        o <= 64'hDEADDEADDEADDEAD;
default:        o <= 64'hDEADDEADDEADDEAD;
endcase
endcase
end
end
 
 
// Generate done signal
// Generate done signal

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