`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Register file with two write ports and six read ports.
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// Register file with two write ports and six read ports.
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// ============================================================================
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// ============================================================================
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//
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//
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module Thor_regfile2w6r(clk, wr0, wr1, wa0, wa1, i0, i1,
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module Thor_regfile2w6r(clk, wr0, wr1, wa0, wa1, i0, i1,
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rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
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rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
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parameter WID=64;
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parameter WID=64;
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input clk;
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input clk;
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input wr0;
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input wr0;
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input wr1;
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input wr1;
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input [5:0] wa0;
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input [7:0] wa0;
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input [5:0] wa1;
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input [7:0] wa1;
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input [WID-1:0] i0;
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input [WID-1:0] i0;
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input [WID-1:0] i1;
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input [WID-1:0] i1;
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input rclk;
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input rclk;
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input [5:0] ra0;
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input [7:0] ra0;
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input [5:0] ra1;
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input [7:0] ra1;
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input [5:0] ra2;
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input [7:0] ra2;
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input [5:0] ra3;
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input [7:0] ra3;
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input [5:0] ra4;
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input [7:0] ra4;
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input [5:0] ra5;
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input [7:0] ra5;
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output [WID-1:0] o0;
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output [WID-1:0] o0;
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output [WID-1:0] o1;
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output [WID-1:0] o1;
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output [WID-1:0] o2;
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output [WID-1:0] o2;
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output [WID-1:0] o3;
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output [WID-1:0] o3;
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output [WID-1:0] o4;
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output [WID-1:0] o4;
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output [WID-1:0] o5;
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output [WID-1:0] o5;
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reg [WID-1:0] regs0 [0:63];
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reg [WID-1:0] regs0 [0:255];
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reg [WID-1:0] regs1 [0:63];
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reg [WID-1:0] regs1 [0:255];
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reg [5:0] rra0,rra1,rra2,rra3,rra4,rra5;
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reg [7:0] rra0,rra1,rra2,rra3,rra4,rra5;
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reg whichreg [0:63]; // tracks which register file is the valid one for a given register
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reg whichreg [0:255]; // tracks which register file is the valid one for a given register
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// We only care about what's in the regs to begin with in simulation. In sim
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// We only care about what's in the regs to begin with in simulation. In sim
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// the 'x' values propagate screwing things up. In real hardware there's no such
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// the 'x' values propagate screwing things up. In real hardware there's no such
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// thing as an 'x'.
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// thing as an 'x'.
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`define SIMULATION
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`define SIMULATION
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`ifdef SIMULATION
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`ifdef SIMULATION
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integer n;
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integer n;
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initial begin
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initial begin
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for (n = 0; n < 64; n = n + 1)
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for (n = 0; n < 64; n = n + 1)
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begin
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begin
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regs0[n] = 0;
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regs0[n] = 0;
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regs1[n] = 0;
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regs1[n] = 0;
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whichreg[n] = 0;
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whichreg[n] = 0;
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end
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end
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end
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end
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`endif
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`endif
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assign o0 = rra0==6'd0 ? {WID{1'b0}} :
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assign o0 = rra0[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra0==wa1)) ? i1 :
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(wr1 && (rra0==wa1)) ? i1 :
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(wr0 && (rra0==wa0)) ? i0 :
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(wr0 && (rra0==wa0)) ? i0 :
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whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
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whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
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assign o1 = rra1==6'd0 ? {WID{1'b0}} :
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assign o1 = rra1[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra1==wa1)) ? i1 :
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(wr1 && (rra1==wa1)) ? i1 :
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(wr0 && (rra1==wa0)) ? i0 :
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(wr0 && (rra1==wa0)) ? i0 :
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whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
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whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
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assign o2 = rra2==6'd0 ? {WID{1'b0}} :
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assign o2 = rra2[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra2==wa1)) ? i1 :
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(wr1 && (rra2==wa1)) ? i1 :
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(wr0 && (rra2==wa0)) ? i0 :
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(wr0 && (rra2==wa0)) ? i0 :
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whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
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whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
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assign o3 = rra3==6'd0 ? {WID{1'b0}} :
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assign o3 = rra3[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra3==wa1)) ? i1 :
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(wr1 && (rra3==wa1)) ? i1 :
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(wr0 && (rra3==wa0)) ? i0 :
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(wr0 && (rra3==wa0)) ? i0 :
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whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
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whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
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assign o4 = rra4==6'd0 ? {WID{1'b0}} :
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assign o4 = rra4[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra4==wa1)) ? i1 :
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(wr1 && (rra4==wa1)) ? i1 :
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(wr0 && (rra4==wa0)) ? i0 :
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(wr0 && (rra4==wa0)) ? i0 :
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whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
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whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
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assign o5 = rra5==6'd0 ? {WID{1'b0}} :
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assign o5 = rra5[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra5==wa1)) ? i1 :
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(wr1 && (rra5==wa1)) ? i1 :
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(wr0 && (rra5==wa0)) ? i0 :
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(wr0 && (rra5==wa0)) ? i0 :
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whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
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whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
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always @(posedge clk)
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always @(posedge clk)
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if (wr0)
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if (wr0)
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regs0[wa0] <= i0;
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regs0[wa0] <= i0;
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always @(posedge clk)
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always @(posedge clk)
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if (wr1)
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if (wr1)
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regs1[wa1] <= i1;
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regs1[wa1] <= i1;
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always @(posedge rclk) rra0 <= ra0;
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always @(posedge rclk) rra0 <= ra0;
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always @(posedge rclk) rra1 <= ra1;
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always @(posedge rclk) rra1 <= ra1;
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always @(posedge rclk) rra2 <= ra2;
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always @(posedge rclk) rra2 <= ra2;
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always @(posedge rclk) rra3 <= ra3;
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always @(posedge rclk) rra3 <= ra3;
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always @(posedge rclk) rra4 <= ra4;
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always @(posedge rclk) rra4 <= ra4;
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always @(posedge rclk) rra5 <= ra5;
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always @(posedge rclk) rra5 <= ra5;
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always @(posedge clk)
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always @(posedge clk)
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// writing three registers at once
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// writing three registers at once
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if (wr0 && wr1 && wa0==wa1) // Two ports writing the same address
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if (wr0 && wr1 && wa0==wa1) // Two ports writing the same address
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whichreg[wa0] <= 1'b1; // port one is the valid one
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whichreg[wa0] <= 1'b1; // port one is the valid one
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// writing two registers
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// writing two registers
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else if (wr0 && wr1) begin
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else if (wr0 && wr1) begin
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whichreg[wa0] <= 1'b0;
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whichreg[wa0] <= 1'b0;
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whichreg[wa1] <= 1'b1;
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whichreg[wa1] <= 1'b1;
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end
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end
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// writing a single register
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// writing a single register
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else if (wr0)
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else if (wr0)
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whichreg[wa0] <= 1'b0;
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whichreg[wa0] <= 1'b0;
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else if (wr1)
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else if (wr1)
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whichreg[wa1] <= 1'b1;
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whichreg[wa1] <= 1'b1;
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endmodule
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endmodule
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