URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [bootrom.vhd] - Diff between revs 40 and 41

Rev 40	Rev 41
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`end bootrom;`	`end bootrom;`

`architecture syn of bootrom is`	`architecture syn of bootrom is`
`constant ROMSIZE: integer := 64;`	`constant ROMSIZE: integer := 64;`
`type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);`	`type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);`
`signal ROM: ROM_TYPE := (x"0801", x"0a01", x"5853", x"0600", x"0402", x"5033", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e16",`	`signal ROM: ROM_TYPE := (x"0801", x"0afd", x"5853", x"0600", x"1600", x"0402", x"5032", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e0c",`
`x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");`	`x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");`
`signal rdata : std_logic_vector(15 downto 0);`	`signal rdata : std_logic_vector(15 downto 0);`
`begin`	`begin`

`rdata <= ROM(to_integer(unsigned(ADDR)));`	`rdata <= ROM(to_integer(unsigned(ADDR)));`