| Line 79... |
Line 79... |
datawrite <= x"0000";
|
datawrite <= x"0000";
|
we <= "00";
|
we <= "00";
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock)
|
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock, port0temp, port0we, DataIn)
|
variable tmp: integer;
|
variable tmp: integer;
|
variable tmp2: integer;
|
variable tmp2: integer;
|
variable found: boolean := false;
|
variable found: boolean := false;
|
begin
|
begin
|
tmp := to_integer(unsigned(addr));
|
tmp := to_integer(unsigned(addr));
|
tmp2 := to_integer(unsigned(Address));
|
tmp2 := to_integer(unsigned(Address));
|
if tmp2 <= 15 then --internal registers/mapped IO
|
if tmp2 <= 15 then --internal registers/mapped IO
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
if WriteWord='0' then
|
if WriteWord='0' then
|
if tmp2=0 then
|
if tmp2=0 then
|
dataread <= x"0000";
|
--dataread <= x"0000";
|
|
|
gen: for I in 0 to 7 loop
|
gen: for I in 0 to 7 loop
|
if WriteEnable='1' then
|
if WriteEnable='1' then
|
if port0we(I)='1' then --1-bit port set to WRITE mode
|
if port0we(I)='1' then --1-bit port set to WRITE mode
|
port0(I) <= DataIn(I);
|
|
|
Port0(I) <= DataIn(I);
|
|
if I=0 then
|
|
-- report string(DataIn(I));
|
|
--assert(DataIn(I)='1') report "XXXXX" severity note;
|
|
--port0(I) <= '1';
|
|
end if;
|
port0temp(I) <= DataIn(I);
|
port0temp(I) <= DataIn(I);
|
|
--dataread(I) <= DataIn(I);
|
else
|
else
|
port0(I) <= 'Z';
|
port0(I) <= 'Z';
|
|
port0temp(I) <= '0';
|
|
--dataread(I) <= port0(I);
|
end if;
|
end if;
|
else --not WE
|
else --not WE
|
if port0we(I)='0' then --1-bit-port set to READ mode
|
if port0we(I)='0' then --1-bit-port set to READ mode
|
dataread(I) <= port0(I);
|
--dataread(I) <= port0(I);
|
else
|
else
|
dataread(I) <= port0temp(I);
|
--dataread(I) <= port0temp(I);
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop gen;
|
end loop gen;
|
elsif tmp2=1 then
|
elsif tmp2=1 then
|
dataread <= x"00" & port0we;
|
--dataread <= x"00" & port0we;
|
if WriteEnable='1' then
|
if WriteEnable='1' then
|
port0we <= DataIn(7 downto 0);
|
port0we <= DataIn(7 downto 0);
|
|
--dataread<=x"00" & DataIn(7 downto 0);
|
setwe: for I in 0 to 7 loop
|
setwe: for I in 0 to 7 loop
|
if DataIn(I)='0' then
|
if DataIn(I)='0' then
|
port0(I) <= 'Z';
|
port0(I) <= 'Z';
|
end if;
|
end if;
|
end loop setwe;
|
end loop setwe;
|
else
|
else
|
dataread <= x"00" & port0we;
|
--dataread <= x"00" & port0we;
|
end if;
|
end if;
|
else
|
else
|
--synthesis off
|
--synthesis off
|
report "Memory address is outside of bounds of RAM and registers" severity warning;
|
report "Memory address is outside of bounds of RAM and registers" severity warning;
|
--synthesis on
|
--synthesis on
|
| Line 132... |
Line 142... |
--synthesis off
|
--synthesis off
|
report "WriteWord is not allowed in register area. Ignoring access" severity warning;
|
report "WriteWord is not allowed in register area. Ignoring access" severity warning;
|
--synthesis on
|
--synthesis on
|
end if;
|
end if;
|
end if;
|
end if;
|
|
dataread <= x"0000";
|
|
outgen: for I in 0 to 7 loop
|
|
if tmp2=0 then
|
|
if port0we(I)='1' then
|
|
if WriteEnable='1' then
|
|
dataread(I) <= DataIn(I);
|
|
else
|
|
dataread(I) <= port0temp(I);
|
|
end if;
|
|
else
|
|
dataread(I) <= port0(I);
|
|
end if;
|
|
elsif tmp2=0 then
|
|
if WriteEnable='1' then
|
|
dataread(I) <= DataIn(I);
|
|
else
|
|
dataread(I) <= port0we(I);
|
|
end if;
|
|
else
|
|
dataread(I) <= '0';
|
|
end if;
|
|
end loop outgen;
|
R1en <= '0';
|
R1en <= '0';
|
R1we <= "00";
|
R1we <= "00";
|
R1in <= x"0000";
|
R1in <= x"0000";
|
R1addr <= x"00";
|
R1addr <= x"00";
|
elsif tmp >= R1START and tmp <= R1END then --RAM bank1
|
elsif tmp >= R1START and tmp <= R1END then --RAM bank1
|
| Line 155... |
Line 187... |
end if;
|
end if;
|
end process;
|
end process;
|
|
|
readdata: process(Address, dataread)
|
readdata: process(Address, dataread)
|
begin
|
begin
|
|
if to_integer(unsigned(Address))>15 then
|
if Address(0) = '0' then
|
if Address(0) = '0' then
|
DataOut <= dataread;
|
DataOut <= dataread;
|
else
|
else
|
DataOut <= x"00" & dataread(15 downto 8);
|
DataOut <= x"00" & dataread(15 downto 8);
|
end if;
|
end if;
|
|
else
|
|
DataOut <= x"00" & dataread(7 downto 0);
|
|
end if;
|
end process;
|
end process;
|
end Behavioral;
|
end Behavioral;
|
No newline at end of file
|
No newline at end of file
|
