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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [ioport.vhd] - Diff between revs 2 and 10
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| Rev 2 |
Rev 10 |
| Line 36... |
Line 36... |
-- port interface
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-- port interface
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PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
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PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
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PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
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PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
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PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
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PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
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-- MODxIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to peripheral
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-- MODxDIR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- direction
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-- MODxOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from peripheral
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rst_n : IN STD_LOGIC
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rst_n : IN STD_LOGIC
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);
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);
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END ioport;
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END ioport;
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ARCHITECTURE beh OF ioport IS
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ARCHITECTURE beh OF ioport IS
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| Line 180... |
Line 176... |
end generate;
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end generate;
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-- PxIN
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-- PxIN
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PxIN <= PnIN;
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PxIN <= PnIN;
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-- MODxOUT
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-- gen_MODxOUT: for i in 0 to 7 generate
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-- begin
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-- MODxOUT_proc: process (rst_n, PxIN, PxSEL)
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-- begin
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-- if rst_n = '0' then
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-- MODxOUT(i) <= '0';
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-- elsif PxSEL(i) = '1' then
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-- MODxOUT(i) <= PxIN(i);
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-- end if;
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-- end process;
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-- end generate;
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irq_en : process(rst_n, clk_s)
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irq_en : process(rst_n, clk_s)
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begin
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begin
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IF (rst_n = '0') THEN
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IF (rst_n = '0') THEN
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IRQ_S <= '0';
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IRQ_S <= '0';
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ELSE
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ELSE
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