-- ************************************************************************
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-- ************************************************************************
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-- * This is a RTL Model of the MSP430 IO ports without interrupt
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-- * This is a RTL Model of the MSP430 IO ports without interrupt
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-- * functionality
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-- * functionality
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-- *
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-- *
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-- * This io-port fits the behavior of the msp430 io-port. The functionality
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-- * This io-port fits the behavior of the msp430 io-port. The functionality
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-- * of the in- and output lines(the output value is also written to the
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-- * of the in- and output lines(the output value is also written to the
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-- * input) is provided by the sgb25v io-pads
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-- * input) is provided by the sgb25v io-pads
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-- *
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-- *
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-- * author: g.panic - IHP, date: 2011-02-07
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-- * author: g.panic - IHP, date: 2011-02-07
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-- * version: 1.1
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-- * version: 1.1
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-- *
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-- *
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-- * Revision:
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-- * Revision:
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-- * changed clock behavior, clock used only in connection with mdbwr_n
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-- * changed clock behavior, clock used only in connection with mdbwr_n
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-- *
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-- *
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-- ************************************************************************
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-- ************************************************************************
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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ENTITY ioport IS
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ENTITY ioport IS
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PORT (
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PORT (
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cs_n : IN STD_LOGIC; -- chip select signal
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cs_n : IN STD_LOGIC; -- chip select signal
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- memory interface
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-- memory interface
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mdbwr_n : IN STD_LOGIC; -- write enable signal
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mdbwr_n : IN STD_LOGIC; -- write enable signal
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mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
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mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
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mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus
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mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus
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mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers
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mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers
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-- interrupt interface
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-- interrupt interface
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irq : out std_logic;
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irq : out std_logic;
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irqAck : in std_logic;
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irqAck : in std_logic;
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-- port interface
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-- port interface
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PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
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PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
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PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
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PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
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PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
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PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
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-- MODxIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to peripheral
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-- MODxDIR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- direction
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-- MODxOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from peripheral
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rst_n : IN STD_LOGIC
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rst_n : IN STD_LOGIC
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);
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);
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END ioport;
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END ioport;
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ARCHITECTURE beh OF ioport IS
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ARCHITECTURE beh OF ioport IS
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SIGNAL PxIN : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIN : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxOUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxOUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxDIR : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxDIR : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxSEL : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxSEL : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIES : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIES : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIE : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIE : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIFG : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL PxIFG : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL IRQ_S : STD_LOGIC;
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SIGNAL IRQ_S : STD_LOGIC;
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SIGNAL CLK_S : STD_LOGIC;
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SIGNAL CLK_S : STD_LOGIC;
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SIGNAL ifg_clk : std_logic_vector(7 downto 0);
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SIGNAL ifg_clk : std_logic_vector(7 downto 0);
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SIGNAL int : std_logic_vector(7 downto 0);
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SIGNAL int : std_logic_vector(7 downto 0);
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BEGIN
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BEGIN
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CLK_S <= clk;
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CLK_S <= clk;
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- INTERRUPTS
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-- INTERRUPTS
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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int_edge_gen: for i in 0 to 7 generate
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int_edge_gen: for i in 0 to 7 generate
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begin
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begin
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process (PxIN(i), PxSEL(i), PxIES(i))
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process (PxIN(i), PxSEL(i), PxIES(i))
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begin
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begin
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if PxSEL(i) = '0' then
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if PxSEL(i) = '0' then
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if PxIES(i) = '0' then
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if PxIES(i) = '0' then
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int(i) <= PxIN(i);
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int(i) <= PxIN(i);
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else
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else
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int(i) <= not(PxIN(i));
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int(i) <= not(PxIN(i));
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end if;
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end if;
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else
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else
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int(i) <= '0';
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int(i) <= '0';
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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-- generate access clocks to PxIFG, CPU acces has priority
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-- generate access clocks to PxIFG, CPU acces has priority
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ifg_clk_gen: for i in 0 to 7 generate
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ifg_clk_gen: for i in 0 to 7 generate
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begin
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begin
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ifg_clk(i) <= not(mdbwr_n) when (cs_n = '0' and mab = "110") else int(i);
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ifg_clk(i) <= not(mdbwr_n) when (cs_n = '0' and mab = "110") else int(i);
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end generate;
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end generate;
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-- write PxIFG
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-- write PxIFG
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PxIFG_gen: for i in 0 to 7 generate
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PxIFG_gen: for i in 0 to 7 generate
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begin
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begin
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write_ifg : PROCESS (rst_n, ifg_clk(i))
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write_ifg : PROCESS (rst_n, ifg_clk(i))
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BEGIN
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BEGIN
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IF rst_n = '0' THEN
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IF rst_n = '0' THEN
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PxIFG(i) <= '0';
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PxIFG(i) <= '0';
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ELSE
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ELSE
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IF (ifg_clk(i)'event and ifg_clk(i) = '1') THEN
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IF (ifg_clk(i)'event and ifg_clk(i) = '1') THEN
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IF cs_n = '0' and mab = "110" THEN
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IF cs_n = '0' and mab = "110" THEN
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IF mdbwr_n = '0' THEN
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IF mdbwr_n = '0' THEN
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PxIFG(i) <= PxIFG(i) and not(mdb_i(i));
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PxIFG(i) <= PxIFG(i) and not(mdb_i(i));
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END IF;
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END IF;
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ELSE
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ELSE
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PxIFG (i) <= '1';
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PxIFG (i) <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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end generate;
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end generate;
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- REGISTERS
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-- REGISTERS
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- write registers
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-- write registers
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- PxDIR
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-- PxDIR
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write_l_proc : PROCESS(rst_n, mdbwr_n)
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write_l_proc : PROCESS(rst_n, mdbwr_n)
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BEGIN
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BEGIN
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IF rst_n = '0' THEN
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IF rst_n = '0' THEN
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PxDIR <= (OTHERS => '0');
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PxDIR <= (OTHERS => '0');
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PxOUT <= (OTHERS => '0');
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PxOUT <= (OTHERS => '0');
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PxSEL <= (OTHERS => '0');
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PxSEL <= (OTHERS => '0');
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PxIES <= (OTHERS => '0');
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PxIES <= (OTHERS => '0');
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PxIE <= (OTHERS => '0');
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PxIE <= (OTHERS => '0');
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ELSE
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ELSE
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if (mdbwr_n'event and mdbwr_n = '0') then
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if (mdbwr_n'event and mdbwr_n = '0') then
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IF cs_n = '0' THEN
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IF cs_n = '0' THEN
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CASE mab IS
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CASE mab IS
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WHEN "000" => PxDIR <= mdb_i;
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WHEN "000" => PxDIR <= mdb_i;
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WHEN "001" => PxOUT <= mdb_i;
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WHEN "001" => PxOUT <= mdb_i;
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WHEN "011" => PxSEL <= mdb_i;
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WHEN "011" => PxSEL <= mdb_i;
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WHEN "100" => PxIES <= mdb_i;
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WHEN "100" => PxIES <= mdb_i;
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WHEN "101" => PxIE <= mdb_i;
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WHEN "101" => PxIE <= mdb_i;
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WHEN others => null;
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WHEN others => null;
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END CASE;
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END CASE;
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end if;
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end if;
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end if;
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end if;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- read registers
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-- read registers
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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mdb_o <= PxDIR when cs_n = '0' and mab = "000" else
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mdb_o <= PxDIR when cs_n = '0' and mab = "000" else
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PxOUT when cs_n = '0' and mab = "001" else
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PxOUT when cs_n = '0' and mab = "001" else
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PxIN when cs_n = '0' and mab = "010" else
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PxIN when cs_n = '0' and mab = "010" else
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PxSEL when cs_n = '0' and mab = "011" else
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PxSEL when cs_n = '0' and mab = "011" else
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PxIES when cs_n = '0' and mab = "100" else
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PxIES when cs_n = '0' and mab = "100" else
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PxIE when cs_n = '0' and mab = "101" else
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PxIE when cs_n = '0' and mab = "101" else
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PxIFG when cs_n = '0' and mab = "110" else
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PxIFG when cs_n = '0' and mab = "110" else
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(others => '0');
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(others => '0');
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- EXTERNAL PORTS
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-- EXTERNAL PORTS
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-------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------
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-- PnOEN
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-- PnOEN
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gen_PnOEN: for i in 0 to 7 generate
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gen_PnOEN: for i in 0 to 7 generate
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begin
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begin
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-- PnOEN(i) <= NOT (MODxDIR(i)) when PxSEL(i) = '1' else NOT (PxDIR(i));
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-- PnOEN(i) <= NOT (MODxDIR(i)) when PxSEL(i) = '1' else NOT (PxDIR(i));
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PnOEN(i) <= PxDIR(i);
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PnOEN(i) <= PxDIR(i);
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end generate;
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end generate;
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-- PnOUT
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-- PnOUT
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gen_PnOUT: for i in 0 to 7 generate
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gen_PnOUT: for i in 0 to 7 generate
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begin
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begin
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-- PnOUT (i) <= MODxIN(i) when PxSEL(i) = '1' else PxOUT(i);
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-- PnOUT (i) <= MODxIN(i) when PxSEL(i) = '1' else PxOUT(i);
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PnOUT(i) <= PxOUT(i);
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PnOUT(i) <= PxOUT(i);
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end generate;
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end generate;
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-- PxIN
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-- PxIN
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PxIN <= PnIN;
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PxIN <= PnIN;
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-- MODxOUT
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-- gen_MODxOUT: for i in 0 to 7 generate
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-- begin
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-- MODxOUT_proc: process (rst_n, PxIN, PxSEL)
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-- begin
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-- if rst_n = '0' then
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-- MODxOUT(i) <= '0';
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-- elsif PxSEL(i) = '1' then
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-- MODxOUT(i) <= PxIN(i);
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-- end if;
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-- end process;
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-- end generate;
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irq_en : process(rst_n, clk_s)
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irq_en : process(rst_n, clk_s)
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begin
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begin
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IF (rst_n = '0') THEN
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IF (rst_n = '0') THEN
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IRQ_S <= '0';
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IRQ_S <= '0';
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ELSE
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ELSE
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if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge
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if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge
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if (irqAck = '1') then
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if (irqAck = '1') then
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IRQ_S <= '0';
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IRQ_S <= '0';
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else
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else
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if ((PxIE(0) = '1' and PxIFG(0) = '1') or (PxIE(1) = '1' and PxIFG(1) = '1') or (PxIE(2) = '1' and PxIFG(2) = '1') or (PxIE(3) = '1' and PxIFG(3) = '1') or
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if ((PxIE(0) = '1' and PxIFG(0) = '1') or (PxIE(1) = '1' and PxIFG(1) = '1') or (PxIE(2) = '1' and PxIFG(2) = '1') or (PxIE(3) = '1' and PxIFG(3) = '1') or
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(PxIE(4) = '1' and PxIFG(4) = '1') or (PxIE(5) = '1' and PxIFG(5) = '1') or (PxIE(6) = '1' and PxIFG(6) = '1') or (PxIE(7) = '1' and PxIFG(7) = '1')) then
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(PxIE(4) = '1' and PxIFG(4) = '1') or (PxIE(5) = '1' and PxIFG(5) = '1') or (PxIE(6) = '1' and PxIFG(6) = '1') or (PxIE(7) = '1' and PxIFG(7) = '1')) then
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IRQ_S <= '1';
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IRQ_S <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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irq <= IRQ_S;
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irq <= IRQ_S;
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END beh;
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END beh;
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