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-------------------------------------------------------------------------------
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--
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-- Design: tinyVLIW8 soft-core processor
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Date: 24.10.2013
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-- File: sysArch_tb.vhd
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--
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-------------------------------------------------------------------------------
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--
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-- Description : System architecture testbench. Using a ROM initialized by
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-- ihex file to simplify system tests.
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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--
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- or - as soon they will be approved by the European Commission - subsequent
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-- versions of the EUPL (the "License").
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-- You may redistribute this code and/or modify it under the terms of this
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-- License.
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-- You may not use this work except in compliance with the License.
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-- You may obtain a copy of the License at:
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--
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-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity sysArch_tb is
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entity sysArch_tb is
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end sysArch_tb;
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end sysArch_tb;
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-- reset input
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-- reset input
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rst_n : in std_logic
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rst_n : in std_logic
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);
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);
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end component;
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end component;
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component symDecoder
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port (
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clk : in std_logic;
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codeA : in std_logic;
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codeB : in std_logic;
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ioAddr : in std_logic_vector(3 downto 0); -- register address
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ioWriteEn_n : in std_logic; -- write enable, low active
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ioReadEn_n : in std_logic; -- read enable, low active
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ioDataOut : out std_logic_vector(7 downto 0); -- data bus for writing register
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ioDataIn : in std_logic_vector(7 downto 0); -- data bus for reading register
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irq : out std_logic;
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irq_ack : in std_logic;
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rst_n : in std_logic
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);
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end component;
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component lib_tb_clock32kHz is
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component lib_tb_clock32kHz is
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port (
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port (
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signal clk : out std_logic;
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signal clk : out std_logic;
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signal rst_n : out std_logic
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signal rst_n : out std_logic
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);
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);
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signal dataOut : out std_logic_vector(31 downto 0);
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signal dataOut : out std_logic_vector(31 downto 0);
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signal en_n : in std_logic
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signal en_n : in std_logic
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);
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);
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end component;
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end component;
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component wurCodeGen_tb is
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port (
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clk : in std_logic;
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pattern : in std_logic_vector(31 downto 0);
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mask : in std_logic_vector(31 downto 0);
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codeA : out std_logic;
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codeB : out std_logic;
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finished : out std_logic;
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rst_n : in std_logic
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);
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end component;
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component gendelay
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component gendelay
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generic (n: integer := 1);
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generic (n: integer := 1);
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port (
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port (
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a_in : in std_logic;
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a_in : in std_logic;
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a_out : out std_logic
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a_out : out std_logic
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signal spiMiso_s : std_logic := '0';
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signal spiMiso_s : std_logic := '0';
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signal dataInClk_s : std_logic;
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signal dataInClk_s : std_logic;
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signal dataOutClk_s : std_logic;
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signal dataOutClk_s : std_logic;
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signal ioSymRdEn_n_s : std_logic;
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signal wurPattern_s : std_Logic_vector(31 downto 0);
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signal wurMsk_s : std_Logic_vector(31 downto 0);
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signal codeA_s : std_logic;
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signal codeB_s : std_logic;
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signal wurCodeEn_n_s : std_logic;
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signal wurCodeFin_s : std_logic;
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signal rst_n_s : std_logic := '1';
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signal rst_n_s : std_logic := '1';
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begin
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begin
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sysArch_i : sysArch
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sysArch_i : sysArch
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stalled_n => stalled_n_s,
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stalled_n => stalled_n_s,
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rst_n => rst_n_s
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rst_n => rst_n_s
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);
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);
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symDecoder_i: symDecoder
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port map (
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clk => clk_s,
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codeA => codeA_s,
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codeB => codeB_s,
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ioAddr => ioAddr_s(3 downto 0),
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ioWriteEn_n => ioWrEn_n_s,
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ioReadEn_n => ioSymRdEn_n_s,
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ioDataOut => ioDataIn_s,
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ioDataIn => ioDataOut_s,
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irq => irqLine_s,
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irq_ack => irqLineAck_s,
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rst_n => rst_n_s
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);
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ioSymRdEn_n_s <= ioRdEn_n_s when ioAddr_s(7 downto 4) = "0100" else
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'1';
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tb_wurCodeGen_i: wurCodeGen_tb
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port map (
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clk => clk_s,
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pattern => wurPattern_s,
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mask => wurMsk_s,
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codeA => codeA_s,
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codeB => codeB_s,
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finished => wurCodeFin_s,
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rst_n => wurCodeEn_n_s
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);
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tb_clock32kHz_i: lib_tb_clock32kHz
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tb_clock32kHz_i: lib_tb_clock32kHz
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port map (
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port map (
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clk => clk_s,
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clk => clk_s,
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rst_n => rst_n_s
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rst_n => rst_n_s
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);
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);
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tb_rom32bit_i: lib_tb_rom32bit
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tb_rom32bit_i: lib_tb_rom32bit
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generic map ( fileName => "../programs/sha1Test.ihex" )
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generic map ( fileName => "../opencores/tinyvliw8/tinyvliw8/trunk/programs/timerIrq.ihex" )
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port map (
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port map (
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addr => instAddr_s,
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addr => instAddr_s,
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dataOut => instData_s,
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dataOut => instData_s,
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en_n => instEn_n_s
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en_n => instEn_n_s
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);
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);
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dataInClk_s <= '1' when (dataEn_n_s = '0' and dataEnDly_n_s = '1' and dataWr_n_s = '1') or
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dataInClk_s <= '1' when (dataEn_n_s = '0' and dataEnDly_n_s = '1' and dataWr_n_s = '1') or
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(dataEn_n_s = '0' and dataEnDly_n_s = '0' and dataWr_n_s = '0') else
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(dataEn_n_s = '0' and dataEnDly_n_s = '0' and dataWr_n_s = '0') else
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'0';
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'0';
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dataOutClk_s <= not(dataInClk_s);
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dataOutClk_s <= not(dataInClk_s);
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wurGen_p : process
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begin
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wurMsk_s <= x"ffffffff";
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wurPattern_s <= x"abababab";
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wurCodeEn_n_s <= '0';
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loop
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wait on rst_n_s;
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exit when rst_n_s = '1';
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end loop;
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loop
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wait for 100 ms;
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wurCodeEn_n_s <= '1';
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loop
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wait on wurCodeFin_s;
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exit when wurCodeFin_s = '1';
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end loop;
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wurCodeEn_n_s <= '0';
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end loop;
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end process;
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end beh;
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end beh;
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No newline at end of file
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No newline at end of file
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