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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 wishbone interface to instruction rom ////
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//// 8051 wishbone interface to instruction rom ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/turb08051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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// initial import
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// initial import
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//
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//
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//
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//
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_wb_iinterface(rst, clk,
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module oc8051_wb_iinterface(rst, clk,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_o, dat_i, cyc_o, stb_o, ack_i
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adr_o, dat_i, cyc_o, stb_o, ack_i
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);
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);
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