URL
https://opencores.org/ocsvn/tv80/tv80/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 105 |
Rev 109 |
| Line 71... |
Line 71... |
wire [1:0] fw_up_ctrl;
|
wire [1:0] fw_up_ctrl;
|
wire dma_iorq_n;
|
wire dma_iorq_n;
|
wire [7:0] dma_rd_data;
|
wire [7:0] dma_rd_data;
|
reg [31:0] read_hold;
|
reg [31:0] read_hold;
|
reg read_latch;
|
reg read_latch;
|
wire dma_int_n; // From dma of mx_lcfg_dma.v
|
|
wire proc_reset_n;
|
wire proc_reset_n;
|
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
|
wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
|
wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
|
wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
|
| Line 99... |
Line 98... |
.A (addr),
|
.A (addr),
|
// Inputs
|
// Inputs
|
.reset_n (proc_reset_n),
|
.reset_n (proc_reset_n),
|
.clk (clk),
|
.clk (clk),
|
.wait_n (wait_n),
|
.wait_n (wait_n),
|
.int_n (dma_int_n),
|
.int_n (1'b1),
|
.nmi_n (1'b1),
|
.nmi_n (1'b1),
|
.busrq_n (1'b1),
|
.busrq_n (1'b1),
|
.di (di));
|
.di (di));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
| Line 206... |
Line 205... |
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
.addr (addr[15:0]),
|
.addr (addr[15:0]),
|
.cd_wdata (dout[7:0]), // Templated
|
.cd_wdata (dout[7:0]), // Templated
|
.mreq_n (mreq_n),
|
|
.rd_n (rd_n),
|
.rd_n (rd_n),
|
.wr_n (wr_n),
|
.wr_n (wr_n),
|
.iorq_n (iorq_n),
|
.iorq_n (iorq_n),
|
.cfgo_trdy (cfgo_trdy),
|
.cfgo_trdy (cfgo_trdy),
|
.cfgo_rd_data (cfgo_rd_data[31:0]));
|
.cfgo_rd_data (cfgo_rd_data[31:0]));
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.