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[/] [tv80/] [trunk/] [rtl/] [app_localcfg/] [lcfg_cfgo_driver.v] - Diff between revs 103 and 105

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Rev 103 Rev 105
Line 72... Line 72...
  always @*
  always @*
    begin
    begin
      nxt_chold = chold;
      nxt_chold = chold;
      nxt_state = state;
      nxt_state = state;
 
 
      case (1'b1)
      case (1'b1) /* verilator lint_off CASEINCOMPLETE */
        state[s_idle] :
        state[s_idle] :
          begin
          begin
            case (wr_stb)
            case (wr_stb)
              4'b0001 : nxt_chold[7:0] = cfg_data0_wr_data;
              4'b0001 : nxt_chold[7:0] = cfg_data0_wr_data;
              4'b0010 : nxt_chold[15:8] = cfg_data1_wr_data;
              4'b0010 : nxt_chold[15:8] = cfg_data1_wr_data;
Line 107... Line 107...
 
 
        state[s_ack] :
        state[s_ack] :
          begin
          begin
            nxt_state = 1 << s_idle;
            nxt_state = 1 << s_idle;
          end
          end
      endcase // case (1'b1)
      endcase // verilator lint_on CASEINCOMPLETE
    end // always @ *
    end // always @ *
 
 
 
  always @(posedge clk or negedge reset_n)
 
    begin
 
      if (~reset_n)
 
        begin
 
          state <= 1 << s_idle;
 
          chold <= 0;
 
        end
 
      else
 
        begin
 
          state <= nxt_state;
 
          chold <= nxt_chold;
 
        end
 
    end
 
 
/* lcfg_cfgo_regs AUTO_TEMPLATE
/* lcfg_cfgo_regs AUTO_TEMPLATE
 (
 (
     .rf_trdy                           (cfgo_wait_n),
     .rf_trdy                           (cfgo_wait_n),
     .rf_rd_data                        (cd_rdata[]),
     .rf_rd_data                        (cd_rdata[]),
Line 123... Line 136...
     .cfg_data0_rd_data (chold[7:0]),
     .cfg_data0_rd_data (chold[7:0]),
     .cfg_data1_rd_data (chold[15:8]),
     .cfg_data1_rd_data (chold[15:8]),
     .cfg_data2_rd_data (chold[23:16]),
     .cfg_data2_rd_data (chold[23:16]),
     .cfg_data3_rd_data (chold[31:24]),
     .cfg_data3_rd_data (chold[31:24]),
     .cfg_data0_rd_ack                  (state[s_ack]),
     .cfg_data0_rd_ack                  (state[s_ack]),
 
     .cfg_status                        ({4'h0, state}),
     .cfg_data[1-3]_rd_ack              (1'b1),
     .cfg_data[1-3]_rd_ack              (1'b1),
     .cfg_data[0-3]_wr_ack              (state[s_idle]),
     .cfg_data[0-3]_wr_ack              (state[s_idle]),
     .cfg_data\([0-3]\)_wr_stb          (wr_stb[\1]),
     .cfg_data\([0-3]\)_wr_stb          (wr_stb[\1]),
     .cfg_data\([0-3]\)_rd_stb          (rd_stb[\1]),
     .cfg_data\([0-3]\)_rd_stb          (rd_stb[\1]),
     .cfg_status ({4'h0,state}),
     .cfg_status ({4'h0,state}),
Line 170... Line 184...
     .cfg_data3_rd_data                 (chold[31:24]),          // Templated
     .cfg_data3_rd_data                 (chold[31:24]),          // Templated
     .cfg_data3_rd_ack                  (1'b1),                  // Templated
     .cfg_data3_rd_ack                  (1'b1),                  // Templated
     .cfg_data3_wr_ack                  (state[s_idle]),         // Templated
     .cfg_data3_wr_ack                  (state[s_idle]),         // Templated
     .cfg_status                        ({4'h0,state}));          // Templated
     .cfg_status                        ({4'h0,state}));          // Templated
endmodule
endmodule
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