| Line 80... |
Line 80... |
reg a_rip, nxt_a_rip; // read in progress by A
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reg a_rip, nxt_a_rip; // read in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg b_rip, nxt_b_rip; // read in progress by B
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reg b_rip, nxt_b_rip; // read in progress by B
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wire t_ram_nwrt, t_ram_nce;
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wire t_ram_nwrt, t_ram_nce;
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wire [35:0] t_ram_din;
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wire [35:0] t_ram_din;
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wire c_rip = lcfg_data_rd_ack;
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wire c_rip = cfgi_trdy;
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wire a_cache_hit, b_cache_hit;
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wire a_cache_hit, b_cache_hit;
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wire [12:0] t_ram_addr;
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wire [12:0] t_ram_addr;
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|
|
/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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| Line 109... |
Line 109... |
.rd_data (dout),
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.rd_data (dout),
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// Inputs
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// Inputs
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.wr_en (!t_ram_nce & !t_ram_nwrt),
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.wr_en (!t_ram_nce & !t_ram_nwrt),
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.rd_en (!t_ram_nce & t_ram_nwrt),
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.rd_en (!t_ram_nce & t_ram_nwrt),
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.clk (clk),
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.clk (clk),
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.wr_data (t_ram_din[]),
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.d_in (t_ram_din[]),
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.addr (t_ram_addr[]),
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.addr (t_ram_addr[]),
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);
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);
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*/
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*/
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|
|
behave1p_mem #(.width(32),
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behave1p_mem #(.width(32),
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| Line 124... |
Line 124... |
.d_out (d_out[31:0]),
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.d_out (d_out[31:0]),
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// Inputs
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// Inputs
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.wr_en (!t_ram_nce & !t_ram_nwrt), // Templated
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.wr_en (!t_ram_nce & !t_ram_nwrt), // Templated
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.rd_en (!t_ram_nce & t_ram_nwrt), // Templated
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.rd_en (!t_ram_nce & t_ram_nwrt), // Templated
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.clk (clk), // Templated
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.clk (clk), // Templated
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.d_in (d_in[31:0]),
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.d_in (t_ram_din[31:0]), // Templated
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.addr (t_ram_addr[12:0])); // Templated
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.addr (t_ram_addr[12:0])); // Templated
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|
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always @*
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always @*
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begin
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begin
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nxt_ca_addr = ca_addr;
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nxt_ca_addr = ca_addr;
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| Line 146... |
Line 146... |
nxt_cvld = cvld;
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nxt_cvld = cvld;
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nxt_wcvld = wcvld;
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nxt_wcvld = wcvld;
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nxt_wc_data = wc_data;
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nxt_wc_data = wc_data;
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nxt_wc_addr = wc_addr;
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nxt_wc_addr = wc_addr;
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nxt_cfgi_trdy = 0;
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nxt_cfgi_trdy = 0;
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//nxt_lcfg_data_rd_ack = 0;
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|
//nxt_lcfg_data_wr_ack = 0;
|
|
|
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if (a_cache_hit)
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if (a_cache_hit)
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begin
|
begin
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case (a_addr[1:0])
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case (a_addr[1:0])
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0 : a_rdata = ca_data[7:0];
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0 : a_rdata = ca_data[7:0];
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| Line 344... |
Line 342... |
if (cfgi_write & !cfgi_trdy)
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if (cfgi_write & !cfgi_trdy)
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begin
|
begin
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nxt_cfgi_trdy = 1;
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nxt_cfgi_trdy = 1;
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ram_nce = 0;
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ram_nce = 0;
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ram_nwrt = 0;
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ram_nwrt = 0;
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ram_addr = lcfg_cfg_addr;
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ram_addr = cfgi_addr;
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ram_din = lcfg_data_wr_data;
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ram_din = cfgi_wr_data;
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// invalidate caches as precaution
|
// invalidate caches as precaution
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nxt_cvld = 0;
|
nxt_cvld = 0;
|
nxt_wcvld = 0;
|
nxt_wcvld = 0;
|
end
|
end
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else if (!cfgi_write & !cfgi_trdy)
|
else if (!cfgi_write & !cfgi_trdy)
|
begin
|
begin
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_addr = lcfg_cfg_addr;
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ram_addr = cfgi_addr;
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nxt_cfgi_trdy = 1;
|
nxt_cfgi_trdy = 1;
|
end
|
end
|
end
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end
|
end
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end
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end // if (lcfg_init)
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end // if (lcfg_init)
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