| Line 21... |
Line 21... |
// Outputs
|
// Outputs
|
a_wait_n, a_rdata, b_wait_n, b_rdata, cfgi_trdy, cfgi_rd_data,
|
a_wait_n, a_rdata, b_wait_n, b_rdata, cfgi_trdy, cfgi_rd_data,
|
// Inputs
|
// Inputs
|
clk, reset_n, a_mreq_n, a_rd_n, a_wr_n, a_addr, a_wdata, b_mreq_n,
|
clk, reset_n, a_mreq_n, a_rd_n, a_wr_n, a_addr, a_wdata, b_mreq_n,
|
b_wr_n, b_addr, b_wdata, lcfg_init, cfgi_irdy, cfgi_addr,
|
b_wr_n, b_addr, b_wdata, lcfg_init, cfgi_irdy, cfgi_addr,
|
cfgi_write, cfgi_wr_data, test_resume_h
|
cfgi_write, cfgi_wr_data
|
);
|
);
|
|
|
|
// address size of memory
|
|
parameter mem_asz = 13, mem_depth = 8192;
|
|
|
input clk;
|
input clk;
|
input reset_n;
|
input reset_n;
|
|
|
// read port A (uP)
|
// read port A (uP)
|
input a_mreq_n;
|
input a_mreq_n;
|
input a_rd_n;
|
input a_rd_n;
|
input a_wr_n;
|
input a_wr_n;
|
input [14:0] a_addr;
|
input [mem_asz+1:0] a_addr;
|
output a_wait_n;
|
output a_wait_n;
|
input [7:0] a_wdata;
|
input [7:0] a_wdata;
|
output [7:0] a_rdata;
|
output [7:0] a_rdata;
|
reg a_wait_n;
|
reg a_wait_n;
|
|
|
// read port B
|
// read port B
|
input b_mreq_n;
|
input b_mreq_n;
|
input b_wr_n;
|
input b_wr_n;
|
input [12:0] b_addr;
|
input [mem_asz-1:0] b_addr;
|
output b_wait_n;
|
output b_wait_n;
|
input [31:0] b_wdata;
|
input [31:0] b_wdata;
|
output [31:0] b_rdata;
|
output [31:0] b_rdata;
|
reg b_wait_n;
|
reg b_wait_n;
|
|
|
| Line 52... |
Line 55... |
|
|
// incoming config interface to
|
// incoming config interface to
|
// read/write processor memory
|
// read/write processor memory
|
input cfgi_irdy;
|
input cfgi_irdy;
|
output cfgi_trdy;
|
output cfgi_trdy;
|
input [14:0] cfgi_addr;
|
input [mem_asz-1:0] cfgi_addr;
|
input cfgi_write;
|
input cfgi_write;
|
input [31:0] cfgi_wr_data;
|
input [31:0] cfgi_wr_data;
|
output [31:0] cfgi_rd_data;
|
output [31:0] cfgi_rd_data;
|
reg cfgi_trdy, nxt_cfgi_trdy;
|
reg cfgi_trdy, nxt_cfgi_trdy;
|
|
|
input test_resume_h;
|
|
|
|
reg ram_nwrt;
|
reg ram_nwrt;
|
reg ram_nce;
|
reg ram_nce;
|
reg [31:0] ram_din;
|
reg [31:0] ram_din;
|
reg [12:0] ram_addr;
|
reg [mem_asz-1:0] ram_addr;
|
wire [31:0] dout;
|
wire [31:0] dout;
|
reg [7:0] a_rdata;
|
reg [7:0] a_rdata;
|
|
|
reg [12:0] ca_addr, nxt_ca_addr;
|
reg [mem_asz-1:0] ca_addr, nxt_ca_addr;
|
reg [31:0] ca_data, nxt_ca_data;
|
reg [31:0] ca_data, nxt_ca_data;
|
reg [12:0] wc_addr, nxt_wc_addr;
|
reg [mem_asz-1:0] wc_addr, nxt_wc_addr;
|
reg [31:0] wc_data, nxt_wc_data;
|
reg [31:0] wc_data, nxt_wc_data;
|
reg cvld, nxt_cvld;
|
reg cvld, nxt_cvld;
|
reg wcvld, nxt_wcvld;
|
reg wcvld, nxt_wcvld;
|
|
|
reg a_prio, nxt_a_prio;
|
reg a_prio, nxt_a_prio;
|
reg a_rip, nxt_a_rip; // read in progress by A
|
reg a_rip, nxt_a_rip; // read in progress by A
|
reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
|
reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
|
reg b_rip, nxt_b_rip; // read in progress by B
|
reg b_rip, nxt_b_rip; // read in progress by B
|
wire t_ram_nwrt, t_ram_nce;
|
wire c_rip = cfgi_trdy;
|
wire [35:0] t_ram_din;
|
|
wire c_rip = cfgi_trdy;
|
wire c_rip = cfgi_trdy;
|
wire a_cache_hit, b_cache_hit;
|
wire a_cache_hit, b_cache_hit;
|
wire [12:0] t_ram_addr;
|
|
|
|
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
|
wire [31:0] d_out; // From mem of behave1p_mem.v
|
|
// End of automatics
|
|
|
|
assign #1 t_ram_nwrt = ram_nwrt;
|
/* -----\/----- EXCLUDED -----\/-----
|
assign #1 t_ram_nce = ram_nce;
|
assign #1 t_ram_nwrt = ram_nwrt;
|
assign #1 t_ram_addr = ram_addr;
|
assign #1 t_ram_nce = ram_nce;
|
assign #1 t_ram_din = ram_din;
|
assign #1 t_ram_addr = ram_addr;
|
|
assign #1 t_ram_din = ram_din;
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
|
assign lcfg_data_rd_data = dout;
|
assign cfgi_rd_data = dout;
|
assign b_rdata = dout;
|
assign b_rdata = dout;
|
|
|
assign a_cache_hit = cvld & (ca_addr == a_addr[14:2]);
|
assign a_cache_hit = cvld & (ca_addr == a_addr[mem_asz+1:2]);
|
assign b_cache_hit = wcvld & (wc_addr == a_addr[14:2]);
|
assign b_cache_hit = wcvld & (wc_addr == a_addr[mem_asz+1:2]);
|
|
|
|
|
/* behave1p_mem AUTO_TEMPLATE
|
/* behave1p_mem AUTO_TEMPLATE
|
(
|
(
|
// Outputs
|
// Outputs
|
.rd_data (dout),
|
.d_out (dout),
|
// Inputs
|
// Inputs
|
.wr_en (!t_ram_nce & !t_ram_nwrt),
|
.wr_en (!ram_nce & !ram_nwrt),
|
.rd_en (!t_ram_nce & t_ram_nwrt),
|
.rd_en (!ram_nce & ram_nwrt),
|
.clk (clk),
|
.clk (clk),
|
.d_in (t_ram_din[]),
|
.d_in (ram_din[]),
|
.addr (t_ram_addr[]),
|
.addr (ram_addr[]),
|
);
|
);
|
*/
|
*/
|
|
|
behave1p_mem #(.width(32),
|
behave1p_mem #(.width(32),
|
.depth (8192),
|
.depth (mem_depth),
|
.addr_sz (13)) mem
|
.addr_sz (mem_asz)) mem
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.d_out (d_out[31:0]),
|
.d_out (dout), // Templated
|
// Inputs
|
// Inputs
|
.wr_en (!t_ram_nce & !t_ram_nwrt), // Templated
|
.wr_en (!ram_nce & !ram_nwrt), // Templated
|
.rd_en (!t_ram_nce & t_ram_nwrt), // Templated
|
.rd_en (!ram_nce & ram_nwrt), // Templated
|
.clk (clk), // Templated
|
.clk (clk), // Templated
|
.d_in (t_ram_din[31:0]), // Templated
|
.d_in (ram_din[31:0]), // Templated
|
.addr (t_ram_addr[12:0])); // Templated
|
.addr (ram_addr[(mem_asz)-1:0])); // Templated
|
|
|
always @*
|
always @*
|
begin
|
begin
|
nxt_ca_addr = ca_addr;
|
nxt_ca_addr = ca_addr;
|
ram_nwrt = 1;
|
ram_nwrt = 1;
|
ram_nce = 1;
|
ram_nce = 1;
|
ram_din = 32'h0;
|
ram_din = 32'h0;
|
ram_addr = a_addr[14:2];
|
ram_addr = a_addr[mem_asz+1:2];
|
a_wait_n = 1;
|
a_wait_n = 1;
|
b_wait_n = 1;
|
b_wait_n = 1;
|
nxt_a_prio = a_prio;
|
nxt_a_prio = a_prio;
|
nxt_a_rip = 0;
|
nxt_a_rip = 0;
|
nxt_b_rip = 0;
|
nxt_b_rip = 0;
|
| Line 201... |
Line 199... |
if (!a_cache_hit & !b_cache_hit)
|
if (!a_cache_hit & !b_cache_hit)
|
begin
|
begin
|
a_wait_n = 0;
|
a_wait_n = 0;
|
if (a_rip)
|
if (a_rip)
|
begin
|
begin
|
nxt_ca_addr = a_addr[14:2];
|
nxt_ca_addr = a_addr[mem_asz+1:2];
|
nxt_ca_data = dout;
|
nxt_ca_data = dout;
|
nxt_cvld = 1;
|
nxt_cvld = 1;
|
end
|
end
|
else if (a_prio | b_mreq_n)
|
else if (a_prio | b_mreq_n)
|
begin
|
begin
|
ram_addr = a_addr[14:2];
|
ram_addr = a_addr[mem_asz+1:2];
|
nxt_a_prio = 0;
|
nxt_a_prio = 0;
|
ram_nce = 0;
|
ram_nce = 0;
|
nxt_a_rip = 1;
|
nxt_a_rip = 1;
|
end
|
end
|
end // if (ca_addr != a_addr[14:2])
|
end // if (ca_addr != a_addr[14:2])
|
| Line 245... |
Line 243... |
// cycle we will get a cache hit.
|
// cycle we will get a cache hit.
|
else if (a_rip)
|
else if (a_rip)
|
begin
|
begin
|
a_wait_n = 0;
|
a_wait_n = 0;
|
nxt_wc_data = dout;
|
nxt_wc_data = dout;
|
nxt_wc_addr = a_addr[14:2];
|
nxt_wc_addr = a_addr[mem_asz+1:2];
|
nxt_wcvld = 1;
|
nxt_wcvld = 1;
|
end
|
end
|
|
|
// if we get a write cache hit, we have the data we
|
// if we get a write cache hit, we have the data we
|
// need. Change the data in the write cache and trigger
|
// need. Change the data in the write cache and trigger
|
| Line 269... |
Line 267... |
// otherwise we do not have the data in our write cache
|
// otherwise we do not have the data in our write cache
|
// yet. Trigger a read to fill the write cache.
|
// yet. Trigger a read to fill the write cache.
|
else if (a_prio | b_mreq_n)
|
else if (a_prio | b_mreq_n)
|
begin
|
begin
|
a_wait_n = 0;
|
a_wait_n = 0;
|
ram_addr = a_addr[14:2];
|
ram_addr = a_addr[mem_asz+1:2];
|
nxt_a_prio = 0;
|
nxt_a_prio = 0;
|
ram_nce = 0;
|
ram_nce = 0;
|
nxt_a_rip = 1;
|
nxt_a_rip = 1;
|
end
|
end
|
end
|
end
|
| Line 342... |
Line 340... |
if (cfgi_write & !cfgi_trdy)
|
if (cfgi_write & !cfgi_trdy)
|
begin
|
begin
|
nxt_cfgi_trdy = 1;
|
nxt_cfgi_trdy = 1;
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_nwrt = 0;
|
ram_nwrt = 0;
|
ram_addr = cfgi_addr;
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
ram_din = cfgi_wr_data;
|
ram_din = cfgi_wr_data;
|
// invalidate caches as precaution
|
// invalidate caches as precaution
|
nxt_cvld = 0;
|
nxt_cvld = 0;
|
nxt_wcvld = 0;
|
nxt_wcvld = 0;
|
end
|
end
|
else if (!cfgi_write & !cfgi_trdy)
|
else if (!cfgi_write & !cfgi_trdy)
|
begin
|
begin
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_addr = cfgi_addr;
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
nxt_cfgi_trdy = 1;
|
nxt_cfgi_trdy = 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end // if (lcfg_init)
|
end // if (lcfg_init)
|
| Line 373... |
Line 371... |
a_rip <= 1'h0;
|
a_rip <= 1'h0;
|
a_wip <= 1'h0;
|
a_wip <= 1'h0;
|
b_rip <= 1'h0;
|
b_rip <= 1'h0;
|
ca_data <= 32'h0;
|
ca_data <= 32'h0;
|
cfgi_trdy <= 1'h0;
|
cfgi_trdy <= 1'h0;
|
wc_addr <= 13'h0;
|
wc_addr <= {mem_asz{1'b0}};
|
wc_data <= 32'h0;
|
wc_data <= 32'h0;
|
wcvld <= 1'h0;
|
wcvld <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end
|
end
|
else
|
else
|
