| Line 80... |
Line 80... |
reg a_prio, nxt_a_prio;
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reg a_prio, nxt_a_prio;
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reg a_rip, nxt_a_rip; // read in progress by A
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reg a_rip, nxt_a_rip; // read in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg b_rip, nxt_b_rip; // read in progress by B
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reg b_rip, nxt_b_rip; // read in progress by B
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wire c_rip = cfgi_trdy;
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wire c_rip = cfgi_trdy;
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wire c_rip = cfgi_trdy;
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wire a_cache_hit, b_cache_hit;
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wire a_cache_hit, b_cache_hit;
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|
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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|
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/* -----\/----- EXCLUDED -----\/-----
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assign #1 t_ram_nwrt = ram_nwrt;
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assign #1 t_ram_nce = ram_nce;
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assign #1 t_ram_addr = ram_addr;
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assign #1 t_ram_din = ram_din;
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-----/\----- EXCLUDED -----/\----- */
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|
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assign cfgi_rd_data = dout;
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assign cfgi_rd_data = dout;
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assign b_rdata = dout;
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assign b_rdata = dout;
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|
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assign a_cache_hit = cvld & (ca_addr == a_addr[mem_asz+1:2]);
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assign a_cache_hit = cvld & (ca_addr == a_addr[mem_asz+1:2]);
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assign b_cache_hit = wcvld & (wc_addr == a_addr[mem_asz+1:2]);
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assign b_cache_hit = wcvld & (wc_addr == a_addr[mem_asz+1:2]);
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| Line 329... |
Line 321... |
end
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end
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end // if (!b_mreq_n)
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end // if (!b_mreq_n)
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|
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if (cfgi_irdy)
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if (cfgi_irdy)
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begin
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begin
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if ((!a_mreq_n | !b_mreq_n) & !c_rip)
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if ((a_mreq_n & b_mreq_n) & !c_rip & !a_wip)
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begin
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// access by A or B ports, stall until memory is free
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end
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else
|
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begin
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begin
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if (cfgi_write & !cfgi_trdy)
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if (cfgi_write & !cfgi_trdy)
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begin
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begin
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nxt_cfgi_trdy = 1;
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nxt_cfgi_trdy = 1;
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ram_nce = 0;
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ram_nce = 0;
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| Line 362... |
Line 350... |
always @(posedge clk or negedge reset_n)
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always @(posedge clk or negedge reset_n)
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begin
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begin
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if (~reset_n)
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if (~reset_n)
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begin
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begin
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ca_addr <= 13'h0;
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ca_addr <= 13'h0;
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cvld <= #1 0;
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cvld <= 0;
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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a_prio <= 1'h0;
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a_prio <= 1'h0;
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a_rip <= 1'h0;
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a_rip <= 1'h0;
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a_wip <= 1'h0;
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a_wip <= 1'h0;
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| Line 378... |
Line 366... |
wcvld <= 1'h0;
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wcvld <= 1'h0;
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// End of automatics
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// End of automatics
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end
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end
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else
|
else
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begin
|
begin
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cvld <= #1 nxt_cvld;
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cvld <= nxt_cvld;
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ca_addr <= #1 nxt_ca_addr;
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ca_addr <= nxt_ca_addr;
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ca_data <= #1 nxt_ca_data;
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ca_data <= nxt_ca_data;
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wcvld <= #1 nxt_wcvld;
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wcvld <= nxt_wcvld;
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wc_addr <= #1 nxt_wc_addr;
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wc_addr <= nxt_wc_addr;
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wc_data <= #1 nxt_wc_data;
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wc_data <= nxt_wc_data;
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a_prio <= #1 nxt_a_prio;
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a_prio <= nxt_a_prio;
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a_rip <= #1 nxt_a_rip;
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a_rip <= nxt_a_rip;
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b_rip <= #1 nxt_b_rip;
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b_rip <= nxt_b_rip;
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a_wip <= #1 nxt_a_wip;
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a_wip <= nxt_a_wip;
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cfgi_trdy <= #1 nxt_cfgi_trdy;
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cfgi_trdy <= nxt_cfgi_trdy;
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end
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end
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end
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end
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endmodule // memcontrol
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endmodule // memcontrol
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