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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_core.v] - Diff between revs 100 and 111
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| Rev 100 |
Rev 111 |
| Line 953... |
Line 953... |
or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
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or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
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or tstate or wait_n)
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or tstate or wait_n)
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begin
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begin
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RegWEH = 1'b0;
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RegWEH = 1'b0;
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RegWEL = 1'b0;
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RegWEL = 1'b0;
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if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
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if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
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(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
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(Save_ALU_r && (ALU_Op_r != 4'b0111)) )
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begin
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begin
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case (Read_To_Reg_r)
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case (Read_To_Reg_r)
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5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
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5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
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begin
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begin
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RegWEH = ~ Read_To_Reg_r[0];
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RegWEH = ~ Read_To_Reg_r[0];
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| Line 968... |
Line 968... |
endcase // case(Read_To_Reg_r)
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endcase // case(Read_To_Reg_r)
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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if (ExchangeDH == 1'b1 && (tstate[3] || tstate[4]) )
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if (ExchangeDH && (tstate[3] || tstate[4]) )
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begin
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begin
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RegWEH = 1'b1;
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RegWEH = 1'b1;
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RegWEL = 1'b1;
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RegWEL = 1'b1;
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end
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end
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if (IncDec_16[2] && ((tstate[2] && ~wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
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if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
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begin
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begin
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case (IncDec_16[1:0])
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case (IncDec_16[1:0])
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2'b00 , 2'b01 , 2'b10 :
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2'b00 , 2'b01 , 2'b10 :
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begin
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begin
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RegWEH = 1'b1;
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RegWEH = 1'b1;
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