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https://opencores.org/ocsvn/uart16750/uart16750/trunk
[/] [uart16750/] [trunk/] [bench/] [vhdl/] [uart_package.vhd] - Diff between revs 17 and 25
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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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);
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);
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-- Compare two std_logig_vectors (handles don't-care)
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-- Compare two std_logig_vectors (handles don't-care)
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
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-- Send serial data to UART
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procedure uart_send (signal sout : out std_logic;
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baud : in time;
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wl : in integer;
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count : in integer;
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file log : TEXT
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);
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end uart_package;
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end uart_package;
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package body uart_package is
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package body uart_package is
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-- Write to UART
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-- Write to UART
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procedure uart_write (signal ui : inout uart_interface;
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procedure uart_write (signal ui : inout uart_interface;
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end if;
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end if;
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end loop;
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end loop;
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return true;
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return true;
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end compare;
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end compare;
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-- Send serial data to UART
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procedure uart_send (signal sout : out std_logic;
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baud : in time;
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wl : in integer;
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count : in integer;
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file log : TEXT
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) is
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variable data : unsigned(7 downto 0);
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begin
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print (log, "UART send: Sending " & integer'image(count) & " symbols with " & integer'image(wl) & " bits");
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data := (others => '0');
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for i in 0 to count loop
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-- Start bit
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sout <= '0';
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wait for baud;
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for i in 0 to wl loop
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sout <= data(i);
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wait for baud;
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end loop;
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-- Stop bit
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sout <= '1';
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wait for baud;
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data := data + 1;
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end loop;
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end uart_send;
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end uart_package;
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end uart_package;
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