--
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--
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-- Package for UART testing
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-- Package for UART testing
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Version: 1.0
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-- Version: 1.0
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-- Date: 31.01.2008
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-- Date: 31.01.2008
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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package uart_package is
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package uart_package is
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constant CYCLE : time := 30 ns;
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constant CYCLE : time := 30 ns;
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-- UART register addresses
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-- UART register addresses
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constant A_RBR : std_logic_vector(2 downto 0) := "000";
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constant A_RBR : std_logic_vector(2 downto 0) := "000";
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constant A_DLL : std_logic_vector(2 downto 0) := "000";
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constant A_DLL : std_logic_vector(2 downto 0) := "000";
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constant A_THR : std_logic_vector(2 downto 0) := "000";
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constant A_THR : std_logic_vector(2 downto 0) := "000";
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constant A_DLM : std_logic_vector(2 downto 0) := "001";
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constant A_DLM : std_logic_vector(2 downto 0) := "001";
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constant A_IER : std_logic_vector(2 downto 0) := "001";
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constant A_IER : std_logic_vector(2 downto 0) := "001";
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constant A_IIR : std_logic_vector(2 downto 0) := "010";
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constant A_IIR : std_logic_vector(2 downto 0) := "010";
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constant A_FCR : std_logic_vector(2 downto 0) := "010";
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constant A_FCR : std_logic_vector(2 downto 0) := "010";
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constant A_LCR : std_logic_vector(2 downto 0) := "011";
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constant A_LCR : std_logic_vector(2 downto 0) := "011";
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constant A_MCR : std_logic_vector(2 downto 0) := "100";
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constant A_MCR : std_logic_vector(2 downto 0) := "100";
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constant A_LSR : std_logic_vector(2 downto 0) := "101";
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constant A_LSR : std_logic_vector(2 downto 0) := "101";
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constant A_MSR : std_logic_vector(2 downto 0) := "110";
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constant A_MSR : std_logic_vector(2 downto 0) := "110";
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constant A_SCR : std_logic_vector(2 downto 0) := "111";
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constant A_SCR : std_logic_vector(2 downto 0) := "111";
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-- UART input interface
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-- UART input interface
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type uart_interface is record
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type uart_interface is record
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CS : std_logic;
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CS : std_logic;
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WR : std_logic;
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WR : std_logic;
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RD : std_logic;
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RD : std_logic;
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A : std_logic_vector (2 downto 0);
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A : std_logic_vector (2 downto 0);
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DATA : std_logic_vector (7 downto 0);
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DATA : std_logic_vector (7 downto 0);
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end record;
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end record;
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-- Write to UART
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-- Write to UART
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procedure uart_write (signal ui : inout uart_interface;
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procedure uart_write (signal ui : inout uart_interface;
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addr : in std_logic_vector (2 downto 0);
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addr : in std_logic_vector (2 downto 0);
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data : in std_logic_vector (7 downto 0);
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data : in std_logic_vector (7 downto 0);
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file log : TEXT
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file log : TEXT
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);
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);
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-- Read from UART
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-- Read from UART
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procedure uart_read (signal ui : inout uart_interface;
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procedure uart_read (signal ui : inout uart_interface;
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addr : in std_logic_vector(2 downto 0);
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addr : in std_logic_vector(2 downto 0);
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ret : out std_logic_vector(7 downto 0);
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ret : out std_logic_vector(7 downto 0);
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file log : TEXT
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file log : TEXT
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);
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);
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-- Compare two std_logig_vectors (handles don't-care)
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-- Compare two std_logig_vectors (handles don't-care)
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
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-- Send serial data to UART
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procedure uart_send (signal sout : out std_logic;
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baud : in time;
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wl : in integer;
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count : in integer;
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file log : TEXT
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);
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end uart_package;
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end uart_package;
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package body uart_package is
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package body uart_package is
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-- Write to UART
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-- Write to UART
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procedure uart_write (signal ui : inout uart_interface;
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procedure uart_write (signal ui : inout uart_interface;
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addr : in std_logic_vector (2 downto 0);
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addr : in std_logic_vector (2 downto 0);
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data : in std_logic_vector (7 downto 0);
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data : in std_logic_vector (7 downto 0);
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file log : TEXT
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file log : TEXT
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) is
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) is
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begin
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begin
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print (log, "UART write: 0x" & hstr(addr) & " : 0x" & hstr(data));
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print (log, "UART write: 0x" & hstr(addr) & " : 0x" & hstr(data));
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wait for cycle;
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wait for cycle;
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assert ui.DATA = "ZZZZZZZZ" report "Data bus not tri-state" severity warning;
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assert ui.DATA = "ZZZZZZZZ" report "Data bus not tri-state" severity warning;
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ui.A <= addr;
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ui.A <= addr;
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ui.DATA <= data;
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ui.DATA <= data;
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ui.CS <= '1';
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ui.CS <= '1';
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wait for cycle;
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wait for cycle;
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ui.WR <= '1';
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ui.WR <= '1';
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wait for cycle;
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wait for cycle;
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ui.WR <= '0';
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ui.WR <= '0';
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ui.CS <= '0';
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ui.CS <= '0';
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ui.DATA <= (others => 'Z');
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ui.DATA <= (others => 'Z');
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end uart_write;
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end uart_write;
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-- Read from UART
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-- Read from UART
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procedure uart_read (signal ui : inout uart_interface;
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procedure uart_read (signal ui : inout uart_interface;
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addr : in std_logic_vector(2 downto 0);
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addr : in std_logic_vector(2 downto 0);
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ret : out std_logic_vector(7 downto 0);
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ret : out std_logic_vector(7 downto 0);
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file log : TEXT
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file log : TEXT
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) is
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) is
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variable data : std_logic_vector(7 downto 0);
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variable data : std_logic_vector(7 downto 0);
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begin
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begin
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wait for cycle;
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wait for cycle;
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assert ui.DATA = "ZZZZZZZZ" report "Data bus not tri-state" severity warning;
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assert ui.DATA = "ZZZZZZZZ" report "Data bus not tri-state" severity warning;
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ui.A <= addr;
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ui.A <= addr;
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ui.CS <= '1';
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ui.CS <= '1';
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wait for cycle;
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wait for cycle;
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ui.RD <= '1';
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ui.RD <= '1';
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wait for cycle;
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wait for cycle;
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data := ui.DATA;
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data := ui.DATA;
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wait for cycle;
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wait for cycle;
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ui.RD <= '0';
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ui.RD <= '0';
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ui.CS <= '0';
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ui.CS <= '0';
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print (log, "UART read: 0x" & hstr(addr) & " : 0x" & hstr(data));
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print (log, "UART read: 0x" & hstr(addr) & " : 0x" & hstr(data));
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ret := data;
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ret := data;
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end uart_read;
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end uart_read;
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-- Compare two std_logig_vectors (handles don't-care)
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-- Compare two std_logig_vectors (handles don't-care)
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean is
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function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean is
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variable i : natural;
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variable i : natural;
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begin
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begin
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for i in d1'range loop
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for i in d1'range loop
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if (not (d1(i)='-' or d2(i)='-')) then
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if (not (d1(i)='-' or d2(i)='-')) then
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if (d1(i)/=d2(i)) then
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if (d1(i)/=d2(i)) then
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return false;
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return false;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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return true;
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return true;
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end compare;
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end compare;
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-- Send serial data to UART
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procedure uart_send (signal sout : out std_logic;
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baud : in time;
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wl : in integer;
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count : in integer;
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file log : TEXT
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) is
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variable data : unsigned(7 downto 0);
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begin
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print (log, "UART send: Sending " & integer'image(count) & " symbols with " & integer'image(wl) & " bits");
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data := (others => '0');
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for i in 0 to count loop
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-- Start bit
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sout <= '0';
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wait for baud;
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for i in 0 to wl loop
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sout <= data(i);
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wait for baud;
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end loop;
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-- Stop bit
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sout <= '1';
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wait for baud;
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data := data + 1;
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end loop;
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end uart_send;
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end uart_package;
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end uart_package;
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