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[/] [uart16750/] [trunk/] [rtl/] [vhdl/] [uart_16750.vhd] - Diff between revs 17 and 24

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Line 1... Line 1... 
--
 
--
 
-- UART 16750
 
-- UART 16750
 
--
 
--
 
-- Author:   Sebastian Witt
 
-- Author:   Sebastian Witt
 
-- Date:     29.01.2008
 
-- Date:     29.01.2008
 
-- Version:  1.4
 
-- Version:  1.5
 
--
 
--
 
-- History:  1.0 - Initial version
 
-- History:  1.0 - Initial version
 
--           1.1 - THR empty interrupt register connected to RST
 
--           1.1 - THR empty interrupt register connected to RST
 
--           1.2 - Registered outputs
 
--           1.2 - Registered outputs
 
--           1.3 - Automatic flow control
 
--           1.3 - Automatic flow control
 
--           1.4 - De-assert IIR FIFO64 when FIFO is disabled
 
--           1.4 - De-assert IIR FIFO64 when FIFO is disabled
 
 
 
--           1.5 - Inverted low active outputs when RST is active
 
--
 
--
 
--
 
--
 
-- This code is free software; you can redistribute it and/or
 
-- This code is free software; you can redistribute it and/or
 
-- modify it under the terms of the GNU Lesser General Public
 
-- modify it under the terms of the GNU Lesser General Public
 
-- License as published by the Free Software Foundation; either
 
-- License as published by the Free Software Foundation; either
Line 969... Line 970... 
 
 
 
 
    -- Output registers
 
    -- Output registers
 
    UART_OUTREGS: process (CLK, RST)
 
    UART_OUTREGS: process (CLK, RST)
 
    begin
 
    begin
 
        if (RST = '1') then
 
        if (RST = '1') then
 
            DDIS     <= '0';
 
            DDIS     <= '1';
 
            BAUDOUTN <= '0';
 
            BAUDOUTN <= '1';
 
            OUT1N    <= '0';
 
            OUT1N    <= '1';
 
            OUT2N    <= '0';
 
            OUT2N    <= '1';
 
            RTSN     <= '0';
 
            RTSN     <= '1';
 
            DTRN     <= '0';
 
            DTRN     <= '1';
 
            SOUT     <= '0';
 
            SOUT     <= '1';
 
        elsif (CLK'event and CLK = '1') then
 
        elsif (CLK'event and CLK = '1') then
 
            -- Default values
 
            -- Default values
 
            DDIS     <= '0';
 
            DDIS     <= '0';
 
            BAUDOUTN <= '0';
 
            BAUDOUTN <= '0';
 
            OUT1N    <= '0';
 
            OUT1N    <= '0';

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