//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// uart test bench
|
// uart test bench
|
//
|
//
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
|
|
module test;
|
module test;
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// include uart tasks
|
// include uart tasks
|
`include "uart_tasks.v"
|
`include "uart_tasks.v"
|
|
|
// internal signal
|
// internal signal
|
reg clock; // global clock
|
reg clock; // global clock
|
reg reset; // global reset
|
reg reset; // global reset
|
reg [6:0] counter;
|
reg [6:0] counter;
|
|
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// test bench implementation
|
// test bench implementation
|
// global signals generation
|
// global signals generation
|
initial
|
initial
|
begin
|
begin
|
counter = 0;
|
counter = 0;
|
clock = 0;
|
clock = 0;
|
reset = 1;
|
reset = 1;
|
#40 reset = 0;
|
#40 reset = 0;
|
end
|
end
|
|
|
// clock generator - 40MHz clock
|
// clock generator - 40MHz clock
|
always
|
always
|
begin
|
begin
|
#12 clock = 0;
|
#12 clock = 0;
|
#13 clock = 1;
|
#13 clock = 1;
|
end
|
end
|
|
|
// test bench dump variables
|
// test bench dump variables
|
initial
|
initial
|
begin
|
begin
|
$dumpfile("test.vcd");
|
$dumpfile("test.vcd");
|
//$dumpall;
|
//$dumpall;
|
$dumpvars(0, test);
|
$dumpvars(0, test);
|
end
|
end
|
|
|
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
// test bench transmitter and receiver
|
// test bench transmitter and receiver
|
// uart transmit - test bench control
|
// uart transmit - test bench control
|
|
|
initial
|
initial
|
begin
|
begin
|
// defualt value of serial output
|
// defualt value of serial output
|
serial_out = 1;
|
serial_out = 1;
|
|
|
// transmit a write command to internal register file
|
// transmit a write command to internal register file
|
// command string: "w 4cd9 1a" + CR
|
// command string: "w 4cd9 1a" + CR
|
send_serial (8'h77, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h77, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h34, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h34, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h63, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h63, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h64, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h64, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h39, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h39, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
// transmit a read command from register file
|
// transmit a read command from register file
|
// command string: "r 1a" + CR
|
// command string: "r 1a" + CR
|
send_serial (8'h72, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h72, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
|
#100;
|
#100;
|
|
|
// delay and finish
|
// delay and finish
|
#900000;
|
#900000;
|
$finish;
|
$finish;
|
end
|
end
|
|
|
// uart receive
|
// uart receive
|
initial
|
initial
|
begin
|
begin
|
// default value for serial receiver and serial input
|
// default value for serial receiver and serial input
|
serial_in = 1;
|
serial_in = 1;
|
get_serial_data = 0; // data received from get_serial task
|
get_serial_data = 0; // data received from get_serial task
|
get_serial_status = 0; // status of get_serial task
|
get_serial_status = 0; // status of get_serial task
|
end
|
end
|
|
|
// serial sniffer loop
|
// serial sniffer loop
|
always
|
always
|
begin
|
begin
|
// call serial sniffer
|
// call serial sniffer
|
get_serial(`BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8);
|
get_serial(`BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8);
|
|
|
// check serial receiver status
|
// check serial receiver status
|
// byte received OK
|
// byte received OK
|
if (get_serial_status & `RECEIVE_RESULT_OK)
|
if (get_serial_status & `RECEIVE_RESULT_OK)
|
begin
|
begin
|
// check if not a control character (above and including space ascii code)
|
// check if not a control character (above and including space ascii code)
|
if (get_serial_data >= 8'h20)
|
if (get_serial_data >= 8'h20)
|
$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, get_serial_data, $time);
|
$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, get_serial_data, $time);
|
else
|
else
|
$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, 8'hb0, $time);
|
$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, 8'hb0, $time);
|
end
|
end
|
|
|
// false start error
|
// false start error
|
if (get_serial_status & `RECEIVE_RESULT_FALSESTART)
|
if (get_serial_status & `RECEIVE_RESULT_FALSESTART)
|
$display("Error (get_char): false start condition at %t", $realtime);
|
$display("Error (get_char): false start condition at %t", $realtime);
|
|
|
// bad parity error
|
// bad parity error
|
if (get_serial_status & `RECEIVE_RESULT_BADPARITY)
|
if (get_serial_status & `RECEIVE_RESULT_BADPARITY)
|
$display("Error (get_char): bad parity condition at %t", $realtime);
|
$display("Error (get_char): bad parity condition at %t", $realtime);
|
|
|
// bad stop bits sequence
|
// bad stop bits sequence
|
if (get_serial_status & `RECEIVE_RESULT_BADSTOP)
|
if (get_serial_status & `RECEIVE_RESULT_BADSTOP)
|
$display("Error (get_char): bad stop bits sequence at %t", $realtime);
|
$display("Error (get_char): bad stop bits sequence at %t", $realtime);
|
end
|
end
|
|
|
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
// device under test
|
// device under test
|
// DUT interface
|
// DUT interface
|
wire [7:0] int_address; // address bus to register file
|
wire [7:0] int_address; // address bus to register file
|
wire [7:0] int_wr_data; // write data to register file
|
wire [7:0] int_wr_data; // write data to register file
|
wire int_write; // write control to register file
|
wire int_write; // write control to register file
|
wire int_read; // read control to register file
|
wire int_read; // read control to register file
|
wire [7:0] int_rd_data; // data read from register file
|
wire [7:0] int_rd_data; // data read from register file
|
|
wire int_req; // bus access request signal
|
|
wire int_gnt; // bus access grant signal
|
wire ser_in; // DUT serial input
|
wire ser_in; // DUT serial input
|
wire ser_out; // DUT serial output
|
wire ser_out; // DUT serial output
|
|
|
// DUT instance
|
// DUT instance
|
uart2bus_top uart2bus1
|
uart2bus_top uart2bus1
|
(
|
(
|
.clock(clock), .reset(reset),
|
.clock(clock), .reset(reset),
|
.ser_in(ser_in), .ser_out(ser_out),
|
.ser_in(ser_in), .ser_out(ser_out),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_rd_data(int_rd_data), .int_read(int_read)
|
.int_rd_data(int_rd_data), .int_read(int_read),
|
|
.int_req(int_req), .int_gnt(int_gnt)
|
);
|
);
|
|
// bus grant is always active
|
|
assign int_gnt = 1'b1;
|
|
|
// serial interface to test bench
|
// serial interface to test bench
|
assign ser_in = serial_out;
|
assign ser_in = serial_out;
|
always @ (posedge clock) serial_in = ser_out;
|
always @ (posedge clock) serial_in = ser_out;
|
|
|
// register file model
|
// register file model
|
reg_file_model reg_file1
|
reg_file_model reg_file1
|
(
|
(
|
.clock(clock), .reset(reset),
|
.clock(clock), .reset(reset),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
|
.int_rd_data(int_rd_data), .int_read(int_read)
|
.int_rd_data(int_rd_data), .int_read(int_read)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
// Th.. Th.. Th.. Thats all folks !!!
|
// Th.. Th.. Th.. Thats all folks !!!
|
//---------------------------------------------------------------------------------------
|
//---------------------------------------------------------------------------------------
|
|
|
