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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [baud_gen.v] - Diff between revs 2 and 3

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// the two registers should be calculated as follows:
// the two registers should be calculated as follows:
// first register:
// first register:
//              baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
//              baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
// second register:
// second register:
//              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
//              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
 
//
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
 
 
module baud_gen
module baud_gen
(
(
        clock, reset,
        clock, reset,

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