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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart2bus_top.v] - Diff between revs 2 and 4
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Rev 4 |
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output int_write; // write control to register file
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output int_write; // write control to register file
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output int_read; // read control to register file
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output int_read; // read control to register file
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input [7:0] int_rd_data; // data read from register file
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input [7:0] int_rd_data; // data read from register file
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// baud rate configuration, see baud_gen.v for more details.
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// baud rate configuration, see baud_gen.v for more details.
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// baud rate generator parameters for 115200 baud on 44MHz clock
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`define D_BAUD_FREQ 12'd23
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`define D_BAUD_LIMIT 16'd527
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// baud rate generator parameters for 115200 baud on 40MHz clock
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// baud rate generator parameters for 115200 baud on 40MHz clock
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//`define D_BAUD_FREQ 12'h90
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`define D_BAUD_FREQ 12'h90
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//`define D_BAUD_LIMIT 16'h0ba5
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`define D_BAUD_LIMIT 16'h0ba5
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// baud rate generator parameters for 115200 baud on 44MHz clock
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// `define D_BAUD_FREQ 12'd23
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// `define D_BAUD_LIMIT 16'd527
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// baud rate generator parameters for 9600 baud on 66MHz clock
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// baud rate generator parameters for 9600 baud on 66MHz clock
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//`define D_BAUD_FREQ 12'h10
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//`define D_BAUD_FREQ 12'h10
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//`define D_BAUD_LIMIT 16'h1ACB
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//`define D_BAUD_LIMIT 16'h1ACB
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// internal wires
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// internal wires
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