URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_rx.v] - Diff between revs 2 and 9

Rev 2	Rev 9
Line 67...	Line 67...
`begin`	`begin`
`if (reset)`	`if (reset)`
`rx_busy <= 1'b0;`	`rx_busy <= 1'b0;`
`else if (~rx_busy & ce_1_mid)`	`else if (~rx_busy & ce_1_mid)`
`rx_busy <= 1'b1;`	`rx_busy <= 1'b1;`
`else if (rx_busy & (bit_count == 4'h9) & ce_1)`	`else if (rx_busy & (bit_count == 4'h8) & ce_1_mid)`
`rx_busy <= 1'b0;`	`rx_busy <= 1'b0;`
`end`	`end`

`// bit counter`	`// bit counter`
`always @ (posedge clock or posedge reset)`	`always @ (posedge clock or posedge reset)`