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https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package helpers_pkg is
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package helpers_pkg is
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procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic);
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procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0));
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component regFileModel
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component regFileModel
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port
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port
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(
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(
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clr : in std_logic;
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clr : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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intRdData : out std_logic_vector(7 downto 0));
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intRdData : out std_logic_vector(7 downto 0));
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end component;
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end component;
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end helpers_pkg;
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end helpers_pkg;
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package body helpers_pkg is
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procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
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variable shiftreg : std_logic_vector(7 downto 0);
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variable bitTime : time;
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begin
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bitTime := 1000 ms / (baud + baud * baudError / 100.0);
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shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
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txd <= '0';
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wait for bitTime;
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for index in 0 to bitnumber loop
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txd <= shiftreg(index);
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wait for bitTime;
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end loop;
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txd <= '1';
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wait for stopbit * bitTime;
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end procedure;
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procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
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variable bitTime : time;
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begin
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bitTime := 1000 ms / (baud + baud * baudError / 100.0);
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wait until (rxd = '0');
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wait for bitTime / 2;
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wait for bitTime;
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for index in 0 to bitnumber loop
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data <= rxd & data(7 downto 1);
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wait for bitTime;
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end loop;
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wait for stopbit * bitTime;
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end procedure;
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end;
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