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[/] [uart2bus/] [trunk/] [vhdl/] [bench/] [uart2BusTop_bin_tb.vhd] - Diff between revs 6 and 11

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-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
-- uart test bench   
-- uart test bench   
--
--
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
use std.textio.all;
use std.textio.all;
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_textio.all;
 
 
 
library work;
 
use work.uart2BusTop_pkg.all;
 
use work.helpers_pkg.all;
 
 
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
-- test bench implementation 
-- test bench implementation 
entity uart2BusTop_bin_tb is
entity uart2BusTop_bin_tb is
end uart2BusTop_bin_tb;
end uart2BusTop_bin_tb;
 
 
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        wait for bitTime;
        wait for bitTime;
      end loop;
      end loop;
      wait for stopbit * bitTime;
      wait for stopbit * bitTime;
    end procedure;
    end procedure;
 
 
  component uart2BusTop
 
    generic
 
    (
 
      AW : integer := 8
 
    );
 
    port
 
    (
 
      clr        : in  std_logic;
 
      clk        : in  std_logic;
 
      serIn      : in  std_logic;
 
      serOut     : out std_logic;
 
      intRdData  : in  std_logic_vector(7 downto 0);
 
      intAddress : out std_logic_vector(AW - 1 downto 0);
 
      intWrData  : out std_logic_vector(7 downto 0);
 
      intWrite   : out std_logic;
 
      intRead    : out std_logic
 
    );
 
  end component;
 
 
 
  component regFileModel
 
    port
 
    (
 
      clr        : in  std_logic;
 
      clk        : in  std_logic;
 
      intAddress : in  std_logic_vector(7 downto 0);
 
      intWrData  : in  std_logic_vector(7 downto 0);
 
      intWrite   : in  std_logic;
 
      intRead    : in  std_logic;
 
      intRdData  : out std_logic_vector(7 downto 0));
 
  end component;
 
 
 
  -- Inputs
  -- Inputs
  signal clr            : std_logic := '0';
  signal clr            : std_logic := '0';
  signal clk            : std_logic := '0';
  signal clk            : std_logic := '0';
  signal serIn          : std_logic := '0';
  signal serIn          : std_logic := '0';
  signal intRdData      : std_logic_vector(7 downto 0) := (others => '0');
  signal intRdData      : std_logic_vector(7 downto 0) := (others => '0');
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  signal intWrData      : std_logic_vector(7 downto 0);
  signal intWrData      : std_logic_vector(7 downto 0);
  signal intWrite       : std_logic;
  signal intWrite       : std_logic;
  signal intRead        : std_logic;
  signal intRead        : std_logic;
  signal recvData       : std_logic_vector(7 downto 0);
  signal recvData       : std_logic_vector(7 downto 0);
  signal newRxData      : std_logic;
  signal newRxData      : std_logic;
 
  signal intAccessReq   : std_logic;
 
  signal intAccessGnt   : std_logic;
 
  signal counter        : integer;
 
 
  constant BAUD_115200  : real := 115200.0;
  constant BAUD_115200  : real := 115200.0;
  constant BAUD_38400   : real := 38400.0;
  constant BAUD_38400   : real := 38400.0;
  constant BAUD_28800   : real := 28800.0;
  constant BAUD_28800   : real := 28800.0;
  constant BAUD_19200   : real := 19200.0;
  constant BAUD_19200   : real := 19200.0;
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      (
      (
        clr => clr,
        clr => clr,
        clk => clk,
        clk => clk,
        serIn => serIn,
        serIn => serIn,
        serOut => serOut,
        serOut => serOut,
 
        intAccessReq => intAccessReq,
 
        intAccessGnt => intAccessGnt,
        intRdData => intRdData,
        intRdData => intRdData,
        intAddress => intAddress,
        intAddress => intAddress,
        intWrData => intWrData,
        intWrData => intWrData,
        intWrite => intWrite,
        intWrite => intWrite,
        intRead => intRead
        intRead => intRead
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      intAddress => intAddress,
      intAddress => intAddress,
      intWrData => intWrData,
      intWrData => intWrData,
      intWrite => intWrite,
      intWrite => intWrite,
      intRead => intRead);
      intRead => intRead);
 
 
 
    -- just to create a delay similar to simulate a bus arbitrer
 
    process (clr, clk)
 
    begin
 
      if (clr = '1') then
 
        intAccessGnt <= '0';
 
        counter <= 0;
 
      elsif (rising_edge(clk)) then
 
        if (counter = 0) then
 
          if ((intAccessReq = '1') and (intAccessGnt = '0')) then
 
            counter <= 500;
 
          end if;
 
          intAccessGnt <= '0';
 
        elsif (counter = 1) then
 
          counter <= counter - 1;
 
          intAccessGnt <= '1';
 
        else
 
          counter <= counter - 1;
 
        end if;
 
      end if;
 
    end process;
 
 
    -- clock generator - 25MHz clock 
    -- clock generator - 25MHz clock 
    process
    process
    begin
    begin
      clk <= '0';
      clk <= '0';
      wait for 20 ns;
      wait for 20 ns;
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    --------------------------------------------------------------------
    --------------------------------------------------------------------
    -- uart transmit - test bench control 
    -- uart transmit - test bench control 
    process
    process
 
 
      type     dataFile is file of character;
      type     dataFile is file of character;
      file     testBinaryFile : dataFile open READ_MODE is "test.bin";
      file     testBinaryFile : dataFile open READ_MODE is "../test.bin";
      variable charBuf        : character;
      variable charBuf        : character;
      variable fileLength     : integer;
      variable fileLength     : integer;
      variable byteIndex      : integer;
      variable byteIndex      : integer;
      variable txLength       : integer;
      variable txLength       : integer;
      variable rxLength       : integer;
      variable rxLength       : integer;

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