Line 4... |
Line 4... |
-----------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------
|
use std.textio.all;
|
use std.textio.all;
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.std_logic_textio.all;
|
|
|
|
library work;
|
library work;
|
use work.uart2BusTop_pkg.all;
|
use work.uart2BusTop_pkg.all;
|
use work.helpers_pkg.all;
|
use work.helpers_pkg.all;
|
|
|
Line 19... |
Line 16... |
entity uart2BusTop_txt_tb is
|
entity uart2BusTop_txt_tb is
|
end uart2BusTop_txt_tb;
|
end uart2BusTop_txt_tb;
|
|
|
architecture behavior of uart2BusTop_txt_tb is
|
architecture behavior of uart2BusTop_txt_tb is
|
|
|
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
|
|
|
|
variable shiftreg : std_logic_vector(7 downto 0);
|
|
variable bitTime : time;
|
|
|
|
begin
|
|
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
|
|
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
|
|
txd <= '0';
|
|
wait for bitTime;
|
|
for index in 0 to bitnumber loop
|
|
txd <= shiftreg(index);
|
|
wait for bitTime;
|
|
end loop;
|
|
txd <= '1';
|
|
wait for stopbit * bitTime;
|
|
end procedure;
|
|
|
|
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
|
|
|
|
variable bitTime : time;
|
|
|
|
begin
|
|
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
|
|
wait until (rxd = '0');
|
|
wait for bitTime / 2;
|
|
wait for bitTime;
|
|
for index in 0 to bitnumber loop
|
|
data <= rxd & data(7 downto 1);
|
|
wait for bitTime;
|
|
end loop;
|
|
wait for stopbit * bitTime;
|
|
end procedure;
|
|
|
|
-- Inputs
|
-- Inputs
|
signal clr : std_logic := '0';
|
signal clr : std_logic := '0';
|
signal clk : std_logic := '0';
|
signal clk : std_logic := '0';
|
signal serIn : std_logic := '0';
|
signal serIn : std_logic := '0';
|
signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
|
signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
|