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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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-- uart test bench
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-- uart test bench
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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use std.textio.all;
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use std.textio.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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library work;
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use work.uart2BusTop_pkg.all;
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use work.helpers_pkg.all;
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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-- test bench implementation
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-- test bench implementation
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entity uart2BusTop_txt_tb is
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entity uart2BusTop_txt_tb is
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end uart2BusTop_txt_tb;
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end uart2BusTop_txt_tb;
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wait for bitTime;
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wait for bitTime;
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end loop;
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end loop;
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wait for stopbit * bitTime;
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wait for stopbit * bitTime;
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end procedure;
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end procedure;
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component uart2BusTop
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generic
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(
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AW : integer := 8
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);
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port
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(
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clr : in std_logic;
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clk : in std_logic;
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serIn : in std_logic;
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serOut : out std_logic;
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intRdData : in std_logic_vector(7 downto 0);
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intAddress : out std_logic_vector(7 downto 0);
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intWrData : out std_logic_vector(7 downto 0);
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intWrite : out std_logic;
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intRead : out std_logic
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);
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end component;
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component regFileModel
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port
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(
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clr : in std_logic;
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clk : in std_logic;
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intAddress : in std_logic_vector(7 downto 0);
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intWrData : in std_logic_vector(7 downto 0);
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intWrite : in std_logic;
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intRead : in std_logic;
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intRdData : out std_logic_vector(7 downto 0));
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end component;
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-- Inputs
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-- Inputs
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signal clr : std_logic := '0';
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signal clr : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal serIn : std_logic := '0';
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signal serIn : std_logic := '0';
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signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
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signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
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signal intWrData : std_logic_vector(7 downto 0);
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signal intWrData : std_logic_vector(7 downto 0);
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signal intWrite : std_logic;
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signal intWrite : std_logic;
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signal intRead : std_logic;
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signal intRead : std_logic;
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signal recvData : std_logic_vector(7 downto 0);
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signal recvData : std_logic_vector(7 downto 0);
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signal newRxData : std_logic;
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signal newRxData : std_logic;
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signal intAccessReq : std_logic;
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signal intAccessGnt : std_logic;
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signal counter : integer;
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constant BAUD_115200 : real := 115200.0;
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constant BAUD_115200 : real := 115200.0;
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constant BAUD_38400 : real := 38400.0;
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constant BAUD_38400 : real := 38400.0;
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constant BAUD_28800 : real := 28800.0;
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constant BAUD_28800 : real := 28800.0;
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constant BAUD_19200 : real := 19200.0;
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constant BAUD_19200 : real := 19200.0;
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(
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(
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clr => clr,
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clr => clr,
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clk => clk,
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clk => clk,
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serIn => serIn,
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serIn => serIn,
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serOut => serOut,
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serOut => serOut,
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intAccessReq => intAccessReq,
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intAccessGnt => intAccessGnt,
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intRdData => intRdData,
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intRdData => intRdData,
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intAddress => intAddress,
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intAddress => intAddress,
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intWrData => intWrData,
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intWrData => intWrData,
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intWrite => intWrite,
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intWrite => intWrite,
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intRead => intRead
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intRead => intRead
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intAddress => intAddress,
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intAddress => intAddress,
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intWrData => intWrData,
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intWrData => intWrData,
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intWrite => intWrite,
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intWrite => intWrite,
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intRead => intRead);
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intRead => intRead);
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-- just to create a delay similar to simulate a bus arbitrer
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process (clr, clk)
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begin
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if (clr = '1') then
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intAccessGnt <= '0';
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counter <= 0;
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elsif (rising_edge(clk)) then
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if (counter = 0) then
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if ((intAccessReq = '1') and (intAccessGnt = '0')) then
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counter <= 500;
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end if;
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intAccessGnt <= '0';
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elsif (counter = 1) then
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counter <= counter - 1;
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intAccessGnt <= '1';
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else
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counter <= counter - 1;
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end if;
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end if;
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end process;
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-- clock generator - 25MHz clock
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-- clock generator - 25MHz clock
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process
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process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for 20 ns;
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wait for 20 ns;
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- uart transmit - test bench control
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-- uart transmit - test bench control
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process
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process
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type dataFile is file of character;
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type dataFile is file of character;
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file testTextFile : dataFile open READ_MODE is "test.txt";
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file testTextFile : dataFile open READ_MODE is "../test.txt";
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variable charBuf : character;
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variable charBuf : character;
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variable data : integer;
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variable data : integer;
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variable tempLine : line;
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begin
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begin
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-- default value of serial output
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-- default value of serial output
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serIn <= '1';
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serIn <= '1';
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-- text mode simulation
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-- text mode simulation
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