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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartRx.vhd] - Diff between revs 10 and 11
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Rev 11 |
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-- uart receive module
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-- uart receive module
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library IEEE;
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_unsigned.ALL;
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entity uartRx is
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entity uartRx is
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port ( clr : in std_logic; -- global reset input
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port ( clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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if (clr = '1') then
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if (clr = '1') then
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rxBusy <= '0';
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rxBusy <= '0';
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((rxBusy = '0') and (ce1Mid = '1')) then
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if ((rxBusy = '0') and (ce1Mid = '1')) then
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rxBusy <= '1';
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rxBusy <= '1';
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elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
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elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1Mid = '1')) then
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rxBusy <= '0';
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rxBusy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- bit counter
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-- bit counter
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