| Line 2... |
Line 2... |
-- uart receive module
|
-- uart receive module
|
--
|
--
|
-----------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.ALL;
|
use ieee.std_logic_1164.ALL;
|
use ieee.std_logic_unsigned.ALL;
|
use ieee.numeric_std.ALL;
|
|
|
entity uartRx is
|
entity uartRx is
|
port ( clr : in std_logic; -- global reset input
|
port ( clr : in std_logic; -- global reset input
|
clk : in std_logic; -- global clock input
|
clk : in std_logic; -- global clock input
|
ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
|
ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
|
| Line 43... |
Line 43... |
if (clr = '1') then
|
if (clr = '1') then
|
count16 <= (others => '0');
|
count16 <= (others => '0');
|
elsif (rising_edge(clk)) then
|
elsif (rising_edge(clk)) then
|
if (ce16 = '1') then
|
if (ce16 = '1') then
|
if ((rxBusy = '1') or (inSync(1) = '0')) then
|
if ((rxBusy = '1') or (inSync(1) = '0')) then
|
count16 <= count16 + 1;
|
count16 <= std_logic_vector(unsigned(count16) + 1);
|
else
|
else
|
count16 <= (others => '0');
|
count16 <= (others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 72... |
Line 72... |
bitCount <= (others => '0');
|
bitCount <= (others => '0');
|
elsif (rising_edge(clk)) then
|
elsif (rising_edge(clk)) then
|
if (rxBusy = '0') then
|
if (rxBusy = '0') then
|
bitCount <= (others => '0');
|
bitCount <= (others => '0');
|
elsif ((rxBusy = '1') and (ce1Mid = '1')) then
|
elsif ((rxBusy = '1') and (ce1Mid = '1')) then
|
bitCount <= bitCount + 1;
|
bitCount <= std_logic_vector(unsigned(bitCount) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
-- data buffer shift register
|
-- data buffer shift register
|
process (clr, clk)
|
process (clr, clk)
|
