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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartTop.vhd] - Diff between revs 6 and 11

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Rev 6 Rev 11
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-- uart top level module  
-- uart top level module  
--
--
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library IEEE;
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
 
 
 
library work;
 
use work.uart2BusTop_pkg.all;
 
 
entity uartTop is
entity uartTop is
  port ( -- global signals
  port ( -- global signals
         clr       : in  std_logic;                     -- global reset input
         clr       : in  std_logic;                     -- global reset input
         clk       : in  std_logic;                     -- global clock input
         clk       : in  std_logic;                     -- global clock input
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         baudClk   : out std_logic);                    -- 
         baudClk   : out std_logic);                    -- 
end uartTop;
end uartTop;
 
 
architecture Behavioral of uartTop is
architecture Behavioral of uartTop is
 
 
  component baudGen
 
    port (
 
      clr       : in  std_logic;
 
      clk       : in  std_logic;
 
      baudFreq  : in  std_logic_vector(11 downto 0);
 
      baudLimit : in  std_logic_vector(15 downto 0);
 
      ce16      : out std_logic);
 
  end component;
 
 
 
  component uartTx
 
    port (
 
      clr : in  std_logic;
 
      clk : in  std_logic;
 
      ce16 : in  std_logic;
 
      txData : in  std_logic_vector(7 downto 0);
 
      newTxData : in  std_logic;
 
      serOut : out  std_logic;
 
      txBusy : out  std_logic);
 
  end component;
 
 
 
  component uartRx
 
    port (
 
      clr       : in  std_logic;
 
      clk       : in  std_logic;
 
      ce16      : in  std_logic;
 
      serIn     : in  std_logic;
 
      rxData    : out std_logic_vector(7 downto 0);
 
      newRxData : out std_logic);
 
  end component;
 
 
 
  signal ce16 : std_logic; -- clock enable at bit rate
  signal ce16 : std_logic; -- clock enable at bit rate
 
 
  begin
  begin
    -- baud rate generator module
    -- baud rate generator module
    bg : baudGen
    bg : baudGen

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