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-- uart transmit module
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-- uart transmit module
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uartTx is
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entity uartTx is
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port ( clr : in std_logic; -- global reset input
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port ( clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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txData : in std_logic_vector(7 downto 0); -- data byte to transmit
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txData : in std_logic_vector(7 downto 0); -- data byte to transmit
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newTxData : in std_logic; -- asserted to indicate that there is a new data byte for transmission
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newTxData : in std_logic; -- asserted to indicate that there is a new data byte for transmission
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serOut : out std_logic; -- serial data output
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serOut : out std_logic; -- serial data output
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txBusy : out std_logic); -- signs that transmitter is busy
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txBusy : out std_logic); -- signs that transmitter is busy
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end uartTx;
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end uartTx;
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architecture Behavioral of uartTx is
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architecture Behavioral of uartTx is
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signal iTxBusy : std_logic;
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signal iTxBusy : std_logic;
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signal ce1 : std_logic; -- clock enable at bit rate
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signal ce1 : std_logic; -- clock enable at bit rate
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signal count16 : std_logic_vector(3 downto 0);
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signal count16 : std_logic_vector(3 downto 0);
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signal bitCount : std_logic_vector(3 downto 0);
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signal bitCount : std_logic_vector(3 downto 0);
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signal dataBuf : std_logic_vector(8 downto 0);
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signal dataBuf : std_logic_vector(8 downto 0);
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begin
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begin
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-- a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
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-- a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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count16 <= (others => '0');
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count16 <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((iTxBusy = '1') and (ce16 = '1')) then
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if ((iTxBusy = '1') and (ce16 = '1')) then
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count16 <= count16 + 1;
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count16 <= count16 + 1;
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elsif (iTxBusy = '0') then
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elsif (iTxBusy = '0') then
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count16 <= (others => '0');
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count16 <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- tx_busy flag
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-- tx_busy flag
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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iTxBusy <= '0';
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iTxBusy <= '0';
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((iTxBusy = '0') and (newTxData = '1')) then
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if ((iTxBusy = '0') and (newTxData = '1')) then
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iTxBusy <= '1';
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iTxBusy <= '1';
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elsif ((iTxBusy = '1') and (bitCount = "1010") and (ce1 = '1')) then
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elsif ((iTxBusy = '1') and (bitCount = "1001") and (ce1 = '1')) then
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iTxBusy <= '0';
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iTxBusy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- output bit counter
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-- output bit counter
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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bitCount <= (others => '0');
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bitCount <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((iTxBusy = '1') and (ce1 = '1')) then
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if ((iTxBusy = '1') and (ce1 = '1')) then
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bitCount <= bitCount + 1;
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bitCount <= bitCount + 1;
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elsif (iTxBusy = '0') then
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elsif (iTxBusy = '0') then
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bitCount <= (others => '0');
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bitCount <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- data shift register
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-- data shift register
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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dataBuf <= (others => '0');
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dataBuf <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if (iTxBusy = '0') then
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if (iTxBusy = '0') then
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dataBuf <= txData & '0';
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dataBuf <= txData & '0';
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elsif ((iTxBusy = '1') and (ce1 = '1')) then
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elsif ((iTxBusy = '1') and (ce1 = '1')) then
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dataBuf <= '1' & dataBuf(8 downto 1);
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dataBuf <= '1' & dataBuf(8 downto 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- output data bit
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-- output data bit
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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serOut <= '1';
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serOut <= '1';
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if (iTxBusy = '1') then
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if (iTxBusy = '1') then
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serOut <= dataBuf(0);
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serOut <= dataBuf(0);
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else
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else
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serOut <= '1';
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serOut <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- ce_1 pulse indicating output data bit should be updated
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-- ce_1 pulse indicating output data bit should be updated
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ce1 <= '1' when ((count16 = "1111") and (ce16 = '1')) else '0';
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ce1 <= '1' when ((count16 = "1111") and (ce16 = '1')) else '0';
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txBusy <= iTxBusy;
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txBusy <= iTxBusy;
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end Behavioral;
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end Behavioral;
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