URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartTx.vhd] - Diff between revs 10 and 11

Rev 10	Rev 11
Line 1...	Line 1...
`-----------------------------------------------------------------------------------------`	`-----------------------------------------------------------------------------------------`
`-- uart transmit module`	`-- uart transmit module`
`--`	`--`
`-----------------------------------------------------------------------------------------`	`-----------------------------------------------------------------------------------------`
`library IEEE;`	`library ieee;`
`use IEEE.STD_LOGIC_1164.ALL;`	`use ieee.std_logic_1164.all;`
`use IEEE.STD_LOGIC_UNSIGNED.ALL;`	`use ieee.std_logic_unsigned.all;`

`entity uartTx is`	`entity uartTx is`
`port ( clr : in std_logic; -- global reset input`	`port ( clr : in std_logic; -- global reset input`
`clk : in std_logic; -- global clock input`	`clk : in std_logic; -- global clock input`
`ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module`	`ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module`