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-- uart transmit module
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-- uart transmit module
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--
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--
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity uartTx is
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entity uartTx is
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port ( clr : in std_logic; -- global reset input
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port ( clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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count16 <= (others => '0');
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count16 <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((iTxBusy = '1') and (ce16 = '1')) then
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if ((iTxBusy = '1') and (ce16 = '1')) then
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count16 <= count16 + 1;
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count16 <= std_logic_vector(unsigned(count16) + 1);
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elsif (iTxBusy = '0') then
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elsif (iTxBusy = '0') then
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count16 <= (others => '0');
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count16 <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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bitCount <= (others => '0');
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bitCount <= (others => '0');
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if ((iTxBusy = '1') and (ce1 = '1')) then
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if ((iTxBusy = '1') and (ce1 = '1')) then
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bitCount <= bitCount + 1;
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bitCount <= std_logic_vector(unsigned(bitCount) + 1);
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elsif (iTxBusy = '0') then
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elsif (iTxBusy = '0') then
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bitCount <= (others => '0');
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bitCount <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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