OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [agent/] [sequence/] [uart_sequence.svh] - Diff between revs 5 and 14

Show entire file | Details | Blame | View Log

Rev 5 Rev 14
Line 762... Line 762...
        _command    == nop;
        _command    == nop;
        (length_data > 1) -> (_reqinc == yes);
        (length_data > 1) -> (_reqinc == yes);
        _arbit      == accept;
        _arbit      == accept;
        _reqack     == yes;
        _reqack     == yes;
      } ;
      } ;
      $display("reached here sequence @time=%0t ,, _mode = %p",$time,trans._mode);
 
      finish_item(trans);
      finish_item(trans);
    endtask:body
    endtask:body
  endclass:seq_3p1
  endclass:seq_3p1
 
 
  // 3.2 Apply UART NOP command with acknowledge request and wrong command
  // 3.2 Apply UART NOP command with acknowledge request and wrong command

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.