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[/] [uart2bus_testbench/] [trunk/] [tb/] [agent/] [transaction/] [uart_transaction.svh] - Diff between revs 2 and 3

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//-----------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------------------
 
//
 
//
 
//                             UART2BUS VERIFICATION
 
//                             UART2BUS VERIFICATION
 
//
 
//
 
//-----------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------------------
 
// CREATOR    : HANY SALAH
 
// CREATOR    : HANY SALAH
 
// PROJECT    : UART2BUS UVM TEST BENCH
 
// PROJECT    : UART2BUS UVM TEST BENCH
 
// UNIT       : TRANSACTION
 
// UNIT       : TRANSACTION
 
//-----------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------------------
 
// TITLE      : UART Transaction
 
// TITLE      : UART Transaction
 
// DESCRIPTION: This
 
// DESCRIPTION: THIS FILE INCLUDES MAIN TRANSACTION ATTRIBUTES, CONSTRAINTS AND DO-COPY OVERRIDE
 
//-----------------------------------------------------------------------------
 
//              FUNCTION
 
 
 
//-------------------------------------------------------------------------------------------------
 
// LOG DETAILS
 
// LOG DETAILS
 
//-------------
 
//-------------
 
// VERSION      NAME        DATE        DESCRIPTION
 
// VERSION      NAME        DATE        DESCRIPTION
 
//    1       HANY SALAH    31122015    FILE CREATION
 
//    1       HANY SALAH    31122015    FILE CREATION
 
//    2       HANY SALAH    01012016    COMPLETE ATTRIBUTES
 
//    2       HANY SALAH    01012016    COMPLETE ATTRIBUTES
 
//-----------------------------------------------------------------------------
 
//    3       HANY SALAH    26012016    ADD VALID TRANSACTION CONSTRAINTS
 
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
 
//    4       HANY SALAH    11022016    IMPROVE BLOCK DESCRIPTION AND ADD CODING COMMENTS
 
// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
 
//-------------------------------------------------------------------------------------------------
 
// CREATOR'S PERMISSION
 
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
 
//-----------------------------------------------------------------------------
 
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
 
 
 
//-------------------------------------------------------------------------------------------------
 
class uart_transaction extends uvm_sequence_item;
 
class uart_transaction extends uvm_sequence_item;
 
 
 
 
 
  // Represent the mode of operation either to be text or command mode
 
  // Represent the mode of operation either to be text or command mode
 
  rand mode        _mode;
 
  rand mode        _mode;
 
 
 
 
 
 
 
  // Represent the wrong prefix forced in wrong mode
 
 
 
  rand byte        wrong_prefix;
 
 
 
 
 
  // Represent the type of space either to be single space or tab
 
  // Represent the type of space either to be single space or tab
 
  rand space_type  _spacetype1,_spacetype2;
 
  rand space_type  _spacetype1,_spacetype2;
 
 
 
 
 
  // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]
 
  // Represent the wrong character used as a white space [Refer To Verification Plan For More
 
 
 
  // Information]
 
  rand  byte        space_wrong1;
 
  rand  byte        space_wrong1;
 
 
 
 
 
  // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]
 
  // Represent the wrong character used as a white space [Refer To Verification Plan For More
 
 
 
  // Information]
 
  rand  byte        space_wrong2;
 
  rand  byte        space_wrong2;
 
 
 
 
 
  // Represent the used data through the stimulus
 
  // Represent the used data through the stimulus
 
  rand  byte       _data [];
 
  rand  byte       _data [];
 
 
 
 
 
 
 
  // Represent the false data that is drivin on the serial output bus through the read command
 
 
 
  // response
 
 
 
  rand  byte       false_data [];
 
 
 
 
 
  // Represent the length of data used through the stimulus
 
  // Represent the length of data used through the stimulus
 
  rand int unsigned length_data;
 
  rand int unsigned length_data;
 
 
 
 
 
  // Represent the type of end of line used
 
  // Represent the type of end of line used
 
  rand eol_type     _eoltype;
 
  rand eol_type     _eoltype;
 
 
 
 
 
  // Represent the wrong character used as an end of line [Refer To Verification Plan For More Information]
 
  // Represent the wrong character used as an end of line [Refer To Verification Plan For More
 
 
 
  // Information]
 
  rand byte         eol_wrong;
 
  rand byte         eol_wrong;
 
 
 
 
 
  // Represent the used address through the stimulus
 
  // Represent the used address through the stimulus
 
  rand bit [15:0]   address;
 
  rand bit [15:0]   address;
 
 
 
 
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  rand char_type    _chartype;
 
  rand char_type    _chartype;
 
 
 
 
 
  // Represent the internal bus state either free or busy
 
  // Represent the internal bus state either free or busy
 
  rand arbit        _arbit;
 
  rand arbit        _arbit;
 
 
 
 
 
  // Represents random idle time
 
  // Represent the request to use false data through the read command.
 
 
 
  rand req          false_data_en;
 
 
 
 
 
 
 
  // Represents random idle time before and after the UART stimulus
 
  rand time         time_before,time_after;
 
  rand time         time_before,time_after;
 
 
 
 
 
 
 
  // Represents the acknowledge byte driven by the DUT
 
  byte            acknowledge;
 
  byte            acknowledge;
 
 
 
 
 
 
 
  // Represent the number of the transaction through the whole sequences
 
 
 
  int             _id;
 
 
 
 
 
 
 
  // Represent the scale that is used to scale the idle time values described above
 
  int unsigned scale = 100;
 
  int unsigned scale = 100;
 
 
 
 
 
  `uvm_object_utils(uart_transaction)
 
  `uvm_object_utils(uart_transaction)
 
 
 
 
 
  function new (string name ="uart_transaction");
 
  function new (string name ="uart_transaction");
 
    super.new(name);
 
    super.new(name);
 
  endfunction: new
 
  endfunction: new
 
 
 
 
 
 
 
  // This constraint limit the size of unbounded data and false data arrays to be in the range
 
 
 
  // between one byte and 256 successive bytes.
 
 
 
  // To make Testbench more simple, the length of data is constrained to be less than or equal
 
 
 
  // 10 bytes.
 
 
 
  // Idle time valu
 
  constraint data_length {
 
  constraint data_length {
 
      _data.size == length_data;
 
      _data.size == length_data;
 
 
 
      false_data.size ==length_data;
 
      length_data <= 10;
 
      length_data <= 10;
 
 
 
      length_data inside {[1:256]};
 
      time_before inside {200,300,400,500,600,700,800,900,1000};
 
      time_before inside {200,300,400,500,600,700,800,900,1000};
 
      time_after  inside {200,300,400,500,600,700,800,900,1000};
 
      time_after  inside {200,300,400,500,600,700,800,900,1000};
 
  }
 
  }
 
 
 
 
 
 
 
  // This constraint is used to constrain the wrong character not to be as the UART standard
 
 
 
  // characters.
 
 
 
  // In case of text command, it is critical to make the white space wrong character
 
 
 
  // not to be simiar to either single space character or Tab space character.Address and Data
 
 
 
  // bytes as well shouldn't be like the standard characters.
 
 
 
  // In case of binary command, it is also critical to make the length byte, address bytes, data
 
 
 
  // bytes similiar to UART standard characters.
 
 
 
  constraint transaction_valid {
 
 
 
      !(space_wrong1 inside {`space,`tab,`w,`W,`bin_prfx,`CR,`LF});
 
 
 
      !(space_wrong2 inside {`space,`tab,`w,`W,`bin_prfx,`CR,`LF});
 
 
 
      !(eol_wrong inside {`space,`tab,`w,`W,`bin_prfx,`CR,`LF});
 
 
 
      if (_mode inside {wrong_mode_text,wrong_mode_bin})
 
 
 
        {
 
 
 
          !(space_wrong1 inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
          !(space_wrong2 inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
          !(address [15:08] inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
          !(address [07:00] inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
          foreach(_data[i])
 
 
 
            !(_data[i] inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
 
 
 
 
          !(length_data inside {`w,`W,`r,`R,`bin_prfx});
 
 
 
 
 
 
 
 
 
 
 
        }
 
 
 
  }
 
 
 
 
 
 
 
  // This constraint is used to re-distribute the random enable bit of the false data usage
 
 
 
  constraint read_data_constraints{
 
 
 
 
 
 
 
      if(_command == read)
 
 
 
      {
 
 
 
        false_data_en dist {no:=8, yes:=2};
 
 
 
      }
 
 
 
  }
 
 
 
 
 
  extern function void do_copy (uvm_object rhs);
 
  extern function void do_copy (uvm_object rhs);
 
 
 
 
 
endclass:uart_transaction
 
endclass:uart_transaction
 
 
 
 
 
 
 
 
 
function void uart_transaction::do_copy (uvm_object rhs);
 
function void uart_transaction::do_copy (uvm_object rhs);
 
  uart_transaction _trans;
 
  uart_transaction _trans;
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  _chartype   =_trans._chartype;
 
  _chartype   =_trans._chartype;
 
  _arbit      =_trans._arbit;
 
  _arbit      =_trans._arbit;
 
  time_before =_trans.time_before;
 
  time_before =_trans.time_before;
 
  time_after  =_trans.time_after;
 
  time_after  =_trans.time_after;
 
  acknowledge = _trans.acknowledge;
 
  acknowledge = _trans.acknowledge;
 
 
 
  wrong_prefix=_trans.wrong_prefix;
 
 
 
  false_data  =_trans.false_data;
 
 
 
  false_data_en =_trans.false_data_en;
 
 
 
  _id           =_trans._id;
 
endfunction:do_copy
 
endfunction:do_copy
 
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