//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : TOP MODULE
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// UNIT : TOP MODULE
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART TOP
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// TITLE : UART TOP
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// DESCRIPTION: THIS TOP MODULE THAT INHERITS THE ALL TESTBENCH COMPONENT AND CONNECT THEM TO DUT.
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// DESCRIPTION: THIS TOP MODULE THAT INHERITS THE ALL TESTBENCH COMPONENT AND CONNECT THEM TO DUT.
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// ALSO INCLUDES THE CLOCK GENERATION MECHANISM.
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// ALSO INCLUDES THE CLOCK GENERATION MECHANISM.
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 11012016 FILE CREATION
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// 1 HANY SALAH 11012016 FILE CREATION
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// 2 HANY SALAH 18022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
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// 2 HANY SALAH 18022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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`include "defin_lib.svh"
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`include "defin_lib.svh"
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`include "uart2bus_top.v"
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`include "uart2bus_top.v"
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module uart_top_tb;
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module uart_top_tb;
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import uvm_pkg::*;
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import uvm_pkg::*;
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import uart_pkg::*;
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import uart_pkg::*;
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`include "uvm_macros.svh"
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`include "uvm_macros.svh"
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// Global System clock
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// Global System clock
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logic clk_glob;
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logic clk_glob;
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// UART clock (1/Baud Rate)
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// UART clock (1/Baud Rate)
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logic clk_uart;
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logic clk_uart;
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// Glocal Asynchronous reset
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// Glocal Asynchronous reset
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logic reset;
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logic reset;
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assign rf_inf.int_req = arb_inf.int_req;
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assign rf_inf.int_req = arb_inf.int_req;
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assign rf_inf.int_gnt = arb_inf.int_gnt;
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assign rf_inf.int_gnt = arb_inf.int_gnt;
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// Initiate UART BFM
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// Initiate UART BFM
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uart_interface uart_inf (.reset(reset),
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uart_interface uart_inf (.reset(reset),
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.clock(clk_uart));
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.clock(clk_uart));
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// Initiate Register File BFM
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// Initiate Register File BFM
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rf_interface rf_inf (.reset(reset),
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rf_interface rf_inf (.reset(reset),
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.clock(clk_glob));
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.clock(clk_glob));
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// Initiate Arbiter BFM
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// Initiate Arbiter BFM
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uart_arbiter arb_inf (.reset (reset),
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uart_arbiter arb_inf (.reset (reset),
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.clock(clk_glob));
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.clock(clk_glob));
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// Initiate Design Under Test DUT
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// Initiate Design Under Test DUT
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uart2bus_top dut( .clock(clk_glob),
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uart2bus_top dut( .clock(clk_glob),
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.reset(reset),
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.reset(reset),
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.ser_in(uart_inf.ser_out),
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.ser_in(uart_inf.ser_out),
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.ser_out(uart_inf.ser_in),
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.ser_out(uart_inf.ser_in),
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.int_address(rf_inf.int_address),
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.int_address(rf_inf.int_address),
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.int_wr_data(rf_inf.int_wr_data),
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.int_wr_data(rf_inf.int_wr_data),
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.int_write(rf_inf.int_write),
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.int_write(rf_inf.int_write),
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.int_rd_data(rf_inf.int_rd_data),
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.int_rd_data(rf_inf.int_rd_data),
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.int_read(rf_inf.int_read),
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.int_read(rf_inf.int_read),
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.int_req(arb_inf.int_req),
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.int_req(arb_inf.int_req),
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//.int_gnt(arb_inf.int_gnt));
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//.int_gnt(arb_inf.int_gnt));
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.int_gnt(1'b1));
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.int_gnt(1'b1));
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initial
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initial
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begin
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begin
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reset = 1'b1;
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reset = 1'b1;
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clk_glob = 1'b0;
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clk_glob = 1'b0;
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clk_uart = 1'b0;
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clk_uart = 1'b0;
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#100;
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#100;
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reset = 1'b0;
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reset = 1'b0;
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end
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end
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// Clock Signals Generator
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// Clock Signals Generator
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initial
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initial
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begin
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begin
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fork
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fork
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forever
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forever
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begin
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begin
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#(`glob_clk_period/2) clk_glob = ~clk_glob;
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#(`glob_clk_period/2) clk_glob = ~clk_glob;
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#((`glob_clk_period/2)+1) clk_glob = ~clk_glob;
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#((`glob_clk_period/2)+1) clk_glob = ~clk_glob;
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end
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end
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forever
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forever
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begin
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begin
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#(`buad_clk_period/2) clk_uart = ~clk_uart;
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#(`buad_clk_period/2) clk_uart = ~clk_uart;
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#((`buad_clk_period/2)+1) clk_uart = ~clk_uart;
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#((`buad_clk_period/2)+1) clk_uart = ~clk_uart;
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end
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end
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join
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join
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end
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end
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initial
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initial
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begin
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begin
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uvm_config_db#(virtual uart_interface)::set(uvm_root::get(), "*", "uart_inf",uart_inf);
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uvm_config_db#(virtual uart_interface)::set(uvm_root::get(), "*", "uart_inf",uart_inf);
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uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
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uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
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uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
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uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
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run_test("write_command_mode");
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end
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end
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