| Line 278... |
Line 278... |
assign modemStatusReg = {1'b0,~rix[1],1'b0,~ctsx[1],deltaDcd, deltaRi, deltaDsr, deltaCts};
|
assign modemStatusReg = {1'b0,~rix[1],1'b0,~ctsx[1],deltaDcd, deltaRi, deltaDsr, deltaCts};
|
assign irqStatusReg = {irq_o,2'b00,irqenc,2'b00};
|
assign irqStatusReg = {irq_o,2'b00,irqenc,2'b00};
|
|
|
// mux the reg outputs
|
// mux the reg outputs
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
begin
|
if (cs) begin
|
case(adr_i)
|
case(adr_i)
|
`UART_TRB: dat_o <= accessCD ? {8'h0,clkdiv} : {24'h0,rx_do}; // receiver holding register
|
`UART_TRB: dat_o <= accessCD ? {8'h0,clkdiv} : {24'h0,rx_do}; // receiver holding register
|
`UART_STAT: dat_o <= {irqStatusReg,modemStatusReg,lineStatusReg,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
|
`UART_STAT: dat_o <= {irqStatusReg,modemStatusReg,lineStatusReg,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
|
`UART_CMD: dat_o <= {cmd3,cmd2,cmd1,cmd0};
|
`UART_CMD: dat_o <= {cmd3,cmd2,cmd1,cmd0};
|
`UART_CTRL: dat_o <= {ctrl3,ctrl2,ctrl1,ctrl0};
|
`UART_CTRL: dat_o <= {ctrl3,ctrl2,ctrl1,ctrl0};
|
endcase
|
endcase
|
end
|
end
|
|
else
|
|
dat_o <= 'd0;
|
|
|
|
|
// register updates
|
// register updates
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
