Subversion Repositories uart6551

        cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,

        cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,

        rxd_i, txd_o, data_present,

        rxd_i, txd_o, data_present,

        rxDRQ_o, txDRQ_o,

        rxDRQ_o, txDRQ_o,

        xclk_i, RxC_i

        xclk_i, RxC_i

);

);

parameter pCounterBits = 24;

parameter pCounterBits = 24;

parameter pFifoSize = 1024;

parameter pFifoSize = 1024;

parameter pClkDiv = 24'd1302;   // 9.6k baud, 200.000MHz clock

parameter pClkDiv = 24'd1302;   // 9.6k baud, 200.000MHz clock

parameter HIGH = 1'b1;

parameter HIGH = 1'b1;

parameter LOW = 1'b0;

parameter LOW = 1'b0;

always @(posedge clk_i)

always @(posedge clk_i)

        clkdiv2 <= selCD ? clkdiv : bclkdiv;

        clkdiv2 <= selCD ? clkdiv : bclkdiv;

always @(posedge clk_i)

always @(posedge clk_i)

if (rst_i)

if (rst_i)

else begin

else begin

        c <= c + 2'd1;

        c <= c + 2'd1;

        if (c >= clkdiv2)

        if (c >= clkdiv2)

                c <= 2'd1;

                c <= 2'd1;

end

end

// Detect an edge on the external clock

// Detect an edge on the external clock

wire rxClkEdge;

wire rxClkEdge;

edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(RxCs[1]), .pe(rxClkEdge), .ne() );

edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(RxCs[1]), .pe(rxClkEdge), .ne() );

if (xClkSrc)            // 16x external clock (xclk)

if (xClkSrc)            // 16x external clock (xclk)

        baud16 <= xclkEdge;

        baud16 <= xclkEdge;

else

else

        baud16 <= ibaud16;

        baud16 <= ibaud16;