URL https://opencores.org/ocsvn/uart6551/uart6551/trunk

Subversion Repositories uart6551

[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Fifo.sv] - Diff between revs 2 and 4

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`// ============================================================================`	`// ============================================================================`
`// __`	`// __`
`// \\__/ o\ (C) 2003-2019 Robert Finch, Waterloo`	`// \\__/ o\ (C) 2003-2021 Robert Finch, Waterloo`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch@finitron.ca`	`// \/_// robfinch@finitron.ca`
`// \|\|`	`// \|\|`
`//`	`//`
`//`	`//`
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`// ============================================================================`	`// ============================================================================`
`//`	`//`
`module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty);`	`module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty);`
`parameter WID=8;`	`parameter WID=8;`
`parameter DEP=16;`	`parameter DEP=16;`
`localparam pCtrBits = $clog2(DEP)-1;`	`localparam pCtrBits = $clog2(DEP-1);`
`input clk;`	`input clk;`
`input rst;`	`input rst;`
`input wr;`	`input wr;`
`input rd;`	`input rd;`
`input [WID-1:0] din;`	`input [WID-1:0] din;`
`output [WID-1:0] dout;`	`output [WID-1:0] dout;`
`output [pCtrBits:0] ctr;`	`output [pCtrBits-1:0] ctr;`
`reg [pCtrBits:0] ctr;`	`reg [pCtrBits-1:0] ctr;`
`output full;`	`output full;`
`output empty;`	`output empty;`

`assign full = ctr=={pCtrBits{1'b1}}-1;`	`assign full = ctr=={pCtrBits{1'b1}}-1;`
`assign empty = ctr=={pCtrBits{1'b1}};`	`assign empty = ctr=={pCtrBits{1'b1}};`