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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Rx.sv] - Diff between revs 8 and 13

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Rev 8	Rev 13
Line 127...	Line 127...
`halfLastBit <= 8'd4;`	`halfLastBit <= 8'd4;`
`else`	`else`
`halfLastBit <= 8'd8;`	`halfLastBit <= 8'd8;`

`// record a global error status`	`// record a global error status`
`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`gerr <= 0;`	`gerr <= 0;`
`else begin`	`else begin`
`if (clearGErr)`	`if (clearGErr)`
`gerr <= perr \| ferr \| bz;`	`gerr <= perr \| ferr \| bz;`
Line 181...	Line 181...

`reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops`	`reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops`
`reg rxdsmp; // majority samples`	`reg rxdsmp; // majority samples`
`reg rdxstart; // for majority style sample solid 3tik-wide sample`	`reg rdxstart; // for majority style sample solid 3tik-wide sample`
`reg [1:0] rxdsum [0:1];`	`reg [1:0] rxdsum [0:1];`
`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (baud16x_ce) begin`	`if (baud16x_ce) begin`
`rxdd <= {rxdd[4:0],rxd};`	`rxdd <= {rxdd[4:0],rxd};`
`if (SamplerStyle == 0) begin`	`if (SamplerStyle == 0) begin`
`rxdsmp <= rxdd[3];`	`rxdsmp <= rxdd[3];`
`rdxstart <= rxdd[4]&~rxdd[3];`	`rdxstart <= rxdd[4]&~rxdd[3];`
Line 197...	Line 197...
`rdxstart <= (rxdsum[0] == 2'b00) & (rxdsum[1] == 2'b11);`	`rdxstart <= (rxdsum[0] == 2'b00) & (rxdsum[1] == 2'b11);`
`end`	`end`
`end`	`end`


`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
state <= `IDLE;	state <= `IDLE;
`else begin`	`else begin`
`if (clear)`	`if (clear)`
state <= `IDLE;	state <= `IDLE;
Line 229...	Line 229...
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`cnt <= 8'h00;`	`cnt <= 8'h00;`
`else begin`	`else begin`
`if (clear)`	`if (clear)`
`cnt <= 8'h00;`	`cnt <= 8'h00;`
Line 252...	Line 252...
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`wf <= 1'b0;`	`wf <= 1'b0;`
`else begin`	`else begin`
`// Clear write flag`	`// Clear write flag`
`wf <= 1'b0;`	`wf <= 1'b0;`
Line 274...	Line 274...
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`t5 <= 1'b0;`	`t5 <= 1'b0;`
`else begin`	`else begin`
`if (wf)`	`if (wf)`
`t5 <= t4;`	`t5 <= t4;`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`full1 <= 1'b0;`	`full1 <= 1'b0;`
`else begin`	`else begin`
`if (wf)`	`if (wf)`
`full1 <= 1'b1;`	`full1 <= 1'b1;`
`else if (pe_rd)`	`else if (pe_rd)`
`full1 <= 1'b0;`	`full1 <= 1'b0;`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`didRd <= 1'b0;`	`didRd <= 1'b0;`
`else begin`	`else begin`
`// set a read flag for later reference`	`// set a read flag for later reference`
`if (pe_rd)`	`if (pe_rd)`
Line 315...	Line 315...
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`rx_data <= 11'h0;`	`rx_data <= 11'h0;`
`else begin`	`else begin`
`if (clear)`	`if (clear)`
`rx_data <= 11'h0;`	`rx_data <= 11'h0;`
Line 336...	Line 336...
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`// Overrun: trying to recieve data when recieve buffer is already full.`	`// Overrun: trying to recieve data when recieve buffer is already full.`
`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`overrun <= 1'b0;`	`overrun <= 1'b0;`
`else begin`	`else begin`
`if (!full)`	`if (!full)`
`overrun <= 1'b0;`	`overrun <= 1'b0;`
Line 356...	Line 356...
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`ferr <= 1'b0;`	`ferr <= 1'b0;`
`else begin`	`else begin`
`if (clear)`	`if (clear)`
`ferr <= 1'b0;`	`ferr <= 1'b0;`

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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Rx.sv] - Diff between revs 8 and 13