| Line 35... |
Line 35... |
// ============================================================================
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// ============================================================================
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//
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//
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`define IDLE 0
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`define IDLE 0
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`define CNT 1
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`define CNT 1
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//`define UART_NO_TX_FIFO 1'b1
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`define UART_NO_TX_FIFO 1'b1
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module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
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module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
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fifoEnable, fifoClear, txBreak,
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fifoEnable, fifoClear, txBreak,
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frameSize, wordLength, parityCtrl, baud16x_ce,
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frameSize, wordLength, parityCtrl, baud16x_ce,
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cts, clear, txd, full, empty, qcnt);
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cts, clear, txd, full, empty, qcnt);
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| Line 67... |
Line 67... |
output [3:0] qcnt; // number of characters queued
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output [3:0] qcnt; // number of characters queued
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reg [7:0] t1;
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reg [7:0] t1;
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reg [11:0] t2;
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reg [11:0] t2;
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reg [11:0] tx_data; // transmit data working reg (raw)
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reg [11:0] tx_data; // transmit data working reg (raw)
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reg state; // state machine state
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typedef enum logic {
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IDLE = 1'b0,
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XMIT
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} state_t;
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state_t state; // state machine state
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reg [7:0] cnt; // baud clock counter
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reg [7:0] cnt; // baud clock counter
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reg rd;
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reg rd;
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reg p1, p2; // parity bit
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reg p1, p2; // parity bit
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assign ack = cyc & cs;
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assign ack = cyc & cs;
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| Line 79... |
Line 83... |
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`ifdef UART_NO_TX_FIFO
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`ifdef UART_NO_TX_FIFO
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reg [7:0] fdo2;
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reg [7:0] fdo2;
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reg empty;
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reg empty;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (awr) fdo2 <= {3'd0,din};
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if (awr) fdo2 <= {3'd0,din};
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always @(posedge clk)
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always_ff @(posedge clk)
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begin
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begin
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if (awr) empty <= 0;
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if (awr) empty <= 0;
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else if (rd) empty <= 1;
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else if (rd) empty <= 1;
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end
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end
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assign full = ~empty;
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assign full = ~empty;
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wire [7:0] fdo = fdo2;
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wire [7:0] fdo = fdo2;
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`else
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`else
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reg [7:0] fdo2;
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reg [7:0] fdo2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (awr) fdo2 <= {3'd0,din};
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if (awr) fdo2 <= {3'd0,din};
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// generate an empty signal for when the fifo is disabled
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// generate an empty signal for when the fifo is disabled
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reg fempty2;
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reg fempty2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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fempty2 <= 1;
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fempty2 <= 1;
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else begin
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else begin
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if (awr) fempty2 <= 0;
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if (awr) fempty2 <= 0;
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else if (rd) fempty2 <= 1;
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else if (rd) fempty2 <= 1;
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| Line 130... |
Line 134... |
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// mask transmit data for word length
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// mask transmit data for word length
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// this mask is needed for proper parity generation
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// this mask is needed for proper parity generation
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integer n;
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integer n;
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reg [7:0] mask;
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reg [7:0] mask;
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always @*
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always_comb
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for (n = 0; n < 8; n = n + 1)
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for (n = 0; n < 8; n = n + 1)
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mask[n] = n < wordLength ? 1'b1 : 1'b0;
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mask[n] = n < wordLength ? 1'b1 : 1'b0;
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always @*
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always_comb
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if (txBreak)
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if (txBreak)
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t1 <= 0;
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t1 <= 0;
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else
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else
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t1 <= fdo & mask;
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t1 <= fdo & mask;
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// compute parity bit
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// compute parity bit
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always @*
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always_comb
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begin
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begin
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case (parityCtrl)
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case (parityCtrl)
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3'b001: p1 <= ~^t1;// odd parity
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3'b001: p1 <= ~^t1;// odd parity
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3'b011: p1 <= ^t1; // even parity
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3'b011: p1 <= ^t1; // even parity
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3'b101: p1 <= 1; // mark bit
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3'b101: p1 <= 1; // mark bit
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| Line 162... |
Line 166... |
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always @(posedge clk)
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always @(posedge clk)
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if (ce) p2 <= p1;
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if (ce) p2 <= p1;
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*/
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*/
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// Insert start, parity bit and stop
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// Insert start, parity bit and stop
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always @*
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always_comb
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case(wordLength)
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case(wordLength)
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4'd5: t2 <= {5'b11111,p1,t1[4:0],1'b0};
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4'd5: t2 <= {5'b11111,p1,t1[4:0],1'b0};
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4'd6: t2 <= {4'b1111,p1,t1[5:0],1'b0};
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4'd6: t2 <= {4'b1111,p1,t1[5:0],1'b0};
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4'd7: t2 <= {3'b111,p1,t1[6:0],1'b0};
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4'd7: t2 <= {3'b111,p1,t1[6:0],1'b0};
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default: t2 <= {2'b11,p1,t1[7:0],1'b0};
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default: t2 <= {2'b11,p1,t1[7:0],1'b0};
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endcase
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endcase
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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state <= `IDLE;
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state <= IDLE;
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else begin
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else begin
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if (clear)
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if (clear)
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state <= `IDLE;
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state <= IDLE;
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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case(state)
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case(state)
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`IDLE:
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IDLE:
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if ((!empty && cts)||txBreak)
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if (((!empty && cts)||txBreak) && cnt==frameSize)
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state <= `CNT;
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state <= XMIT;
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`CNT:
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XMIT:
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if (cnt==frameSize)
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if (cnt==frameSize-1)
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state <= `IDLE;
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state <= IDLE;
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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cnt <= 8'h00;
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cnt <= 8'h00;
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else begin
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else begin
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if (clear)
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if (clear)
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cnt <= 8'h00;
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cnt <= 8'h00;
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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case(state)
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if (cnt==frameSize)
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`IDLE:
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cnt <= 8'h0;
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cnt <= 8'h00;
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else
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`CNT:
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cnt <= cnt + 8'd1;
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cnt <= cnt + 8'd1;
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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rd <= 0;
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rd <= 0;
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else begin
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else begin
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rd <= 0;
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rd <= 0;
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if (clear)
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if (clear)
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rd <= 0;
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rd <= 0;
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if (baud16x_ce) begin
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if (baud16x_ce)
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case(state)
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case(state)
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`IDLE:
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IDLE:
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if ((!empty && cts)||txBreak)
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if (((!empty && cts)||txBreak) && cnt==frameSize)
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rd <= 1;
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rd <= 1;
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default: ;
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endcase
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endcase
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end
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end
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end
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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tx_data <= 12'hFFF;
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tx_data <= 12'hFFF;
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else begin
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else begin
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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case(state)
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case(state)
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`IDLE:
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IDLE:
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if ((!empty && cts)||txBreak)
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if (((!empty && cts)||txBreak) && cnt==frameSize)
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tx_data <= t2;
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tx_data <= t2;
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`CNT:
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XMIT:
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// Shift the data out. LSB first.
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// Shift the data out. LSB first.
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if (cnt[3:0]==4'hF)
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if (cnt[3:0]==4'hF)
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tx_data <= {1'b1,tx_data[11:1]};
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tx_data <= {1'b1,tx_data[11:1]};
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always_ff @(posedge clk)
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if (rst)
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if (rst)
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txd <= 1'b1;
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txd <= 1'b1;
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else
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else
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txd <= tx_data[0];
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txd <= tx_data[0];
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