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https://opencores.org/ocsvn/uart8systemc/uart8systemc/trunk
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Rev 7 |
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public:
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public:
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/*Constructor*/
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/*Constructor*/
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Control_SC();
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Control_SC();
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/*initialize systemC model*/
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/*initialize systemC model*/
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virtual void init();
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//virtual void init();
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/*Reset the model*/
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/*Reset the model*/
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virtual void reset_set_high();
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virtual bool reset_set();
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virtual void reset_set_low();
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virtual void clear_validation();
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/*This is used to configure clock on systemC model note here you must put period T = 1/F*/
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/*Finish Simulation*/
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virtual void set_period_clock_sc(unsigned value_freq);
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virtual unsigned int finish_simulation();
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/**/
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virtual unsigned int set_clock_rtl();
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virtual bool enable_change();
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/*This must be used to set baud value on Env. Ex: 9600 / 50MHz"Only 50"*/
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virtual void set_baud_rate(unsigned int value_baud,unsigned frequency);
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/*Get the baud rate and set it to your DUT*/
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/*Get the baud rate and set it to your DUT*/
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virtual int get_baud_rate();
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virtual int get_baud_rate();
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/*We use functions to retreive values from RX / TX SytemC to Verilog*/
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/*We use functions to retreive values from RX / TX SytemC to Verilog*/
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virtual void write_rx(unsigned int a);
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virtual void write_rx(unsigned int a);
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virtual int read_tx();
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virtual int read_tx();
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/**/
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virtual void get_value_sc_vlog(unsigned int value,unsigned int parity);
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/*Run the Env for a mmount off time*/
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/*Run the Env for a mmount off time*/
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virtual void run_sim();
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virtual void run_sim();
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/*Tell to SystemC to finish*/
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/*Tell to SystemC to finish*/
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virtual void stop_sim();
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virtual void stop_sim();
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